tcl/fpga: add Lattice MachXO3 family support

[fw/openocd] / tcl / target / nrf51.cfg

diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 129060d356105dd32856eeb764901d4effdc0db8..48c2715d1003c2940221902c459f1421eed1af4d 100644 (file)
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -1,5 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
-# script for Nordic nRF51 series, a CORTEX-M0 chip
+# script for Nordic nRF51 series, a Cortex-M0 chip
 #
 
 source [find target/swj-dp.tcl]
@@ -17,11 +19,11 @@ if { [info exists ENDIAN] } {
 }
 
 # Work-area is a space in RAM used for flash programming
-# By default use 2kB
+# By default use 16kB
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x800
+   set _WORKAREASIZE 0x4000
 }
 
 if { [info exists CPUTAPID] } {
@@ -31,9 +33,10 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -49,7 +52,7 @@ flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
 #  The chip should start up from internal 16Mhz RC, so setting adapter
 #  clock to 1Mhz should be OK
 #
-adapter_khz 1000
+adapter speed 1000
 
 proc enable_all_ram {} {
        # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks