# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
#
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M4_TAPID
-
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
# LPC4370 has 96+32 KB contiguous SRAM
if { [info exists WORKAREASIZE] } {
jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M0_JTAG_TAPID
- target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
- target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
+ dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
+ dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
+ target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
+ target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
# 32+8+32 KB SRAM
$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \