Change reset configuration.

[fw/openocd] / tcl / target / lpc4350.cfg

diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg
index 6614383b89dff72a0e71f3f1ee2e1d9c9f075dcb..fbbea97d7ff802ab602ec88cacd973b056e99843 100644 (file)
--- a/tcl/target/lpc4350.cfg
+++ b/tcl/target/lpc4350.cfg
@@ -43,6 +43,9 @@ jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
 target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
 target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m3 reset_config sysresetreq
+# on this CPU we should use VECTRESET to perform a soft reset and
+# manually reset the periphery
+# SRST or SYSRESETREQ disable the debug interface for the time of
+# the reset and will not fit our requirements for a consistent debug
+# session
+cortex_m3 reset_config vectreset