rename jtag_nsrst_delay as adapter_nsrst_delay

[fw/openocd] / tcl / target / lpc2478.cfg

diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 2c8fdce33b717baca87ae8d9c1757e9624327ef9..950ef63fd5ba8bdc3ff8f2b47b5a753ea3413892 100644 (file)
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -19,7 +19,7 @@ if { [info exists CPUTAPID ] } {
 }
 
 #delays on reset lines
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
 jtag_ntrst_delay 100
 
 # LPC2000 -> SRST causes TRST
@@ -31,11 +31,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
 
 # LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 0
 
 $_TARGETNAME configure -event reset-init {
        # Force target into ARM state
-       soft_reset_halt
+       arm core_state arm
        # Do not remap 0x0000-0x0020 to anything but the Flash
        mwb 0xE01FC040 0x01
 }
@@ -43,7 +43,8 @@ $_TARGETNAME configure -event reset-init {
 # LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
 # After reset the chip uses its internal 4MHz RC oscillator.
 # flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x7D000 0 0 $_TARGETNAME lpc2000_v2 12000 calc_checksum
 
 # Try to use RCLK, if RCLK is not available use "normal" mode. 4MHz / 6 = 666kHz, so use 500.
 jtag_rclk 500