+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
#
# !!!!!!
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
# delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
if {[using_jtag]} {
jtag_ntrst_delay 200
}