mips: optimize write code for speed

[fw/openocd] / tcl / target / lpc17xx.cfg

diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg
index 379bcfb93e31846ead8feea14ec09e312a9b577d..a64783dab2e75edb6119b5552eb7a8dc5785be71 100644 (file)
--- a/tcl/target/lpc17xx.cfg
+++ b/tcl/target/lpc17xx.cfg
@@ -91,3 +91,7 @@ $_TARGETNAME configure -event reset-init {
 
        mww 0x400FC040 0x01
 }
+
+# if srst is not fitted use VECTRESET to
+# perform a soft reset - SYSRESETREQ is not supported
+cortex_m3 reset_config vectreset