-# Main file for NXP LPC17xx Cortex-M3
-#
-# !!!!!!
-#
-# This file should not be included directly, rather
-# by the lpc1751.cfg, lpc1752.cfg, etc. which set the
-# needed variables to the appropriate values.
-#
-# !!!!!!
+# SPDX-License-Identifier: GPL-2.0-or-later
-# LPC17xx chips support both JTAG and SWD transports.
-# Adapt based on what transport is active.
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- error "_CHIPNAME not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
-}
-
-# After reset the chip is clocked by the ~4MHz internal RC oscillator.
-# When board-specific code (reset-init handler or device firmware)
-# configures another oscillator and/or PLL0, set CCLK to match; if
-# you don't, then flash erase and write operations may misbehave.
-# (The ROM code doing those updates cares about core clock speed...)
-#
-# CCLK is the core clock frequency in KHz
-if { [info exists CCLK] } {
- set _CCLK $CCLK
-} else {
- set _CCLK 4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- error "_CPUTAPID not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
-}
-
-if { [info exists CPURAMSIZE] } {
- set _CPURAMSIZE $CPURAMSIZE
-} else {
- error "_CPURAMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
-}
-
-if { [info exists CPUROMSIZE] } {
- set _CPUROMSIZE $CPUROMSIZE
-} else {
- error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
-}
-
-#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-# The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
-
-# The LPC17xx devies have 32/64/128/256/512kB of flash memory, managed by ROM code
-# (including a boot loader which verifies the flash exception table's checksum).
-# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
- lpc1700 $_CCLK calc_checksum
-
-# Run with *real slow* clock by default since the
-# boot rom could have been playing with the PLL, so
-# we have no idea what clock the target is running at.
-adapter_khz 10
-
-# delays on reset lines
-adapter_nsrst_delay 200
-if {$using_jtag} {
- jtag_ntrst_delay 200
-}
-
-$_TARGETNAME configure -event reset-init {
- # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
- # Bit Symbol Value Description Reset
- # value
- # 0 MAP Memory map control. 0
- # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
- # 1 User mode. The on-chip Flash memory is mapped to address 0.
- # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
- #
- # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
-
- mww 0x400FC040 0x01
+# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
+set CHIPNAME lpc17xx
+set CHIPSERIES lpc1700
+if { ![info exists WORKAREASIZE] } {
+ set WORKAREASIZE 0x2000
}
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+source [find target/lpc1xxx.cfg]
projects / fw / openocd / blobdiff