Add STM32F2X/STLINK target config file.

[fw/openocd] / tcl / target / lpc1768.cfg

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index ff92e4a7bad9b92424b0914157804fc318396906..d1734ddb11c854c0c0c9145e1cf24f175fb4c442 100644 (file)
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -1,9 +1,13 @@
 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
 
+# LPC17xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
-       set  _CHIPNAME $CHIPNAME
+       set _CHIPNAME $CHIPNAME
 } else {
-       set  _CHIPNAME lpc1768
+       set _CHIPNAME lpc1768
 }
 
 # After reset the chip is clocked by the ~4MHz internal RC oscillator.
@@ -13,12 +17,12 @@ if { [info exists CHIPNAME] } {
 # (The ROM code doing those updates cares about core clock speed...)
 #
 # CCLK is the core clock frequency in KHz
-if { [info exists CCLK ] } {
+if { [info exists CCLK] } {
        set _CCLK $CCLK
 } else {
        set _CCLK 4000
 }
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
        set _CPUTAPID $CPUTAPID
 } else {
        set _CPUTAPID 0x4ba00477
@@ -28,10 +32,8 @@ if { [info exists CPUTAPID ] } {
 adapter_nsrst_delay 200
 jtag_ntrst_delay 200
 
-# LPC2000 & LPC1700 -> SRST causes TRST
-reset_config srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
@@ -47,16 +49,10 @@ set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME \
        lpc1700 $_CCLK calc_checksum
 
-# JTAG clock should be CCLK/6 (unless using adaptive clocking)
-# CCLK is 4 MHz after reset, and until board-specific code (like
-# a reset-init handler) speeds it up.
-#
-# Although rclk "appears to work", it turns out that this yields
-# 4MHz whereas the "correct" rate is CCLK/6, which is not what
-# you get with rclk.
-jtag_khz [ expr 4000 / 6 ]
-
-
+# Run with *real slow* clock by default since the
+# boot rom could have been playing with the PLL, so
+# we have no idea what clock the target is running at.
+adapter_khz 10
 
 $_TARGETNAME configure -event reset-init {
        # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select