swj-dp.tcl (SWD infrastructure #1)

[fw/openocd] / tcl / target / lpc1768.cfg

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 4a1ff0bcc4fc7c5e46cc9dd2d084ca2325a838e1..68b33c4bb55ec15c360f719d61f1ede1e9fe9bb8 100644 (file)
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -1,5 +1,9 @@
 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
 
+# LPC17xx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
        set  _CHIPNAME $CHIPNAME
 } else {
@@ -31,7 +35,8 @@ jtag_ntrst_delay 200
 # LPC2000 & LPC1700 -> SRST causes TRST
 reset_config srst_pulls_trst
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+#jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME