cfg: add srst_nogate to the supported targets, remove from board configs

[fw/openocd] / tcl / target / kl25.cfg

diff --git a/tcl/target/kl25.cfg b/tcl/target/kl25.cfg
index c5dda151512f4ad3b1fd92bae89964c491eb9ba6..b75e0a565d776f0c9c4aa1f6f17f60e110a8f797 100644 (file)
--- a/tcl/target/kl25.cfg
+++ b/tcl/target/kl25.cfg
@@ -38,11 +38,34 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_CHIPNAME.cpu
 
+# It is important that "kinetis mdm check_security" is called for
+# 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
+# causes "kinetis mdm check_security" to fail the first time openocd
+# calls it when it tries to connect after the CPU has been power-cycled.
+$_CHIPNAME.cpu configure -event examine-end {
+       kinetis mdm check_security
+}
+
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
+# specifies up to 1MHz for VLPR mode.
+adapter_khz 1000
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+    # Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
+    # specifies up to 24MHz for run mode; Table 17 of Sub-Family Data
+    # Sheet rev4 lists 25MHz as the maximum frequency.
+    adapter_khz 24000
+}