flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAA

[fw/openocd] / tcl / target / imx51.cfg

diff --git a/tcl/target/imx51.cfg b/tcl/target/imx51.cfg
index 706875d3737b614c9fc5d430bb2bd4e440aefbfd..22af2843eed922661774947794d199756c139425 100644 (file)
--- a/tcl/target/imx51.cfg
+++ b/tcl/target/imx51.cfg
@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } {
    set _DAP_TAPID 0x1ba00477
 }
 
-jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
         -expected-id $_DAP_TAPID
 
 # SDMA / no IDCODE
-jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
 
 # SJC
 if { [info exists SJC_TAPID] } {
@@ -26,26 +26,20 @@ if { [info exists SJC_TAPID] } {
    set _SJC_TAPID 0x0190c01d
 }
 
-jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
         -expected-id $_SJC_TAPID -ignore-version
 
 # GDB target: Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
-
-# have the DAP "always" be active
-jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
 
 proc imx51_dbginit {target} {
-     # General Cortex A8 debug initialisation
-     cortex_a8 dbginit
+     # General Cortex-A8 debug initialisation
+     cortex_a dbginit
 }
 
-# Slow speed to be sure it will work
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
-
 $_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"