tcl/target: add SPDX tag

[fw/openocd] / tcl / target / imx31.cfg

diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index 3fed2f820316cc2215d7a975a057a92238708670..10e9fefc01d197979757923fea63d902c4a9a6e9 100644 (file)
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -1,49 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # imx31 config
 #
 
-reset_config trst_and_srst
+reset_config trst_and_srst srst_gates_jtag
+
+adapter srst delay 5
 
-if { [info exists CHIPNAME] } {        
-   set  _CHIPNAME $CHIPNAME    
-} else {        
-   set  _CHIPNAME imx31
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME imx31
 }
 
-if { [info exists ENDIAN] } {  
-   set  _ENDIAN $ENDIAN    
-} else {        
-   set  _ENDIAN little
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x07b3601d
 }
 
-if { [info exists SDMATAPID ] } {
+if { [info exists SDMATAPID] } {
    set _SDMATAPID $SDMATAPID
 } else {
    set _SDMATAPID 0x2190101d
 }
 
-#========================================
-# The "system jtag controller" 
-# IMX31 reference manual, page 6-28 - figure 6-14
-if { [info exists SJCTAPID ] } {
-   set _SJCTAPID $SJCTAPID
+if { [info exists ETBTAPID] } {
+   set _ETBTAPID $ETBTAPID
 } else {
-   set _SJCTAPID 0x2b900f0f
+   set _ETBTAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
+
+#========================================
+
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
 
 # The "SDMA" - <S>mart <DMA> controller debug tap
 # Based on some IO pins - this can be disabled & removed
 # See diagram: 6-14
 #   SIGNAL NAME:
 #    SJC_MOD - controls multiplexer - disables ARM1136
-#    SDMA_BYPASS - disables SDMA    - 
-#  
+#    SDMA_BYPASS - disables SDMA    -
+#
 # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
 
@@ -54,9 +58,13 @@ jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected
 # But this conflicts with Diagram 6-13, "3bits ir and drs"
 jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 
-proc power_restore {} { puts "Sensed power restore. No action." } 
-proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+proc power_restore {} { echo "Sensed power restore. No action." }
+proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb