+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Hisilicon Hi6220 Target
if { [info exists CHIPNAME] } {
}
# declare the one JTAG tap to access the DAP
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
# declare the 8 main application cores
set _TARGETNAME $_CHIPNAME.cpu
set _cores 8
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+ cti create cti$_core -dap $_CHIPNAME.dap -baseaddr [set $_TARGETNAME.cti($_core)] -ap-num 0
+
set _command "target create ${_TARGETNAME}$_core aarch64 \
- -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
+ -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
if { $_core != 0 } {
# non-boot core examination may fail
eval $_smp_command
+cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80003000
+
# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
-target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 2 -defer-examine
+target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+# declare the auxiliary Cortex-A7 core
+target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine