tcl/target: add SPDX tag

[fw/openocd] / tcl / target / gp326xxxa.cfg

diff --git a/tcl/target/gp326xxxa.cfg b/tcl/target/gp326xxxa.cfg
index e801cc8dc517ba7781d81c4cfbdc4cb7eb07decb..447460bf829c2e2a71217bd5c675e56cece76bb2 100644 (file)
--- a/tcl/target/gp326xxxa.cfg
+++ b/tcl/target/gp326xxxa.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Support for General Plus GP326XXXA chips
 #
@@ -24,7 +26,7 @@ jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CP
 
 set _TARGETNAME $_CHIPNAME.cpu
 
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # Use internal SRAM as a work area
 $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
@@ -33,11 +35,11 @@ $_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-a
 reset_config trst_and_srst srst_pulls_trst
 # This delay is needed otherwise communication with the target would
 # be unreliable
-adapter_nsrst_delay 100
+adapter srst delay 100
 
 # Set the adapter speed ridiculously low just in case we are
 # running off of a 32kHz clock
-adapter_khz 2
+adapter speed 2
 
 proc gp32xxxa_halt_and_reset_control_registers {} {
        # System control registers
@@ -57,7 +59,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
        # Set the adapter speed ridiculously low just in case we are
        # running off of a 32kHz clock
-       adapter_khz 2
+       adapter speed 2
 
        # Disable any advanced features at this stage
        arm7_9 dcc_downloads disable
@@ -86,7 +88,7 @@ proc gp32xxxa_halt_and_reset_control_registers {} {
 
        # Now that we know that we are running at 48Mhz
        # Increase JTAG speed and enable speed optimization features
-       adapter_khz 5000
+       adapter speed 5000
        arm7_9 dcc_downloads enable
        arm7_9 fast_memory_access enable
 }