+# SPDX-License-Identifier: GPL-2.0-or-later
+
#
# Utility code for DaVinci-family chips
#
-# davinci_pinmux: assigns PINMUX$reg <== $value
+# davinci_pinmux: assigns PINMUX$reg <== $value
proc davinci_pinmux {soc reg value} {
- mww [expr [dict get $soc sysbase] + 4 * $reg] $value
-}
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
- set value ""
- ocd_mem2array value 32 $reg 1
- return $value(0)
+ mww [expr {[dict get $soc sysbase] + 4 * $reg}] $value
}
-# mmw: "memory modify word", updates value of $reg
-# $reg <== ((value & ~$clearbits) | $setbits)
-proc mmw {reg setbits clearbits} {
- set old [mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww $reg $new
-}
+source [find mem_helper.tcl]
#
# pll_setup: initialize PLL
#
# PLL version 0x02: tested on dm355
-# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
+# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
proc pll_v02_setup {pll_addr mult config} {
- set pll_ctrl_addr [expr $pll_addr + 0x100]
+ set pll_ctrl_addr [expr {$pll_addr + 0x100}]
set pll_ctrl [mrw $pll_ctrl_addr]
# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
- # NOTE: this assumes we should clear that bit
- set pll_ctrl [expr $pll_ctrl & ~0x0100]
+ # NOTE: this assumes we should clear that bit
+ set pll_ctrl [expr {$pll_ctrl & ~0x0100}]
mww $pll_ctrl_addr $pll_ctrl
# 2 - clear PLLENSRC (bit 5)
- set pll_ctrl [expr $pll_ctrl & ~0x0020]
+ set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
mww $pll_ctrl_addr $pll_ctrl
# 3 - clear PLLEN (bit 0) ... enter bypass mode
- set pll_ctrl [expr $pll_ctrl & ~0x0001]
+ set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
mww $pll_ctrl_addr $pll_ctrl
# 4 - wait at least 4 refclk cycles
sleep 1
# 5 - set PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl | 0x0008]
+ set pll_ctrl [expr {$pll_ctrl | 0x0008}]
mww $pll_ctrl_addr $pll_ctrl
# 6 - set PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl | 0x0010]
+ set pll_ctrl [expr {$pll_ctrl | 0x0010}]
mww $pll_ctrl_addr $pll_ctrl
# 7 - clear PLLPWRDN (bit 1)
- set pll_ctrl [expr $pll_ctrl & ~0x0002]
+ set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
mww $pll_ctrl_addr $pll_ctrl
# 8 - clear PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl & ~0x0010]
+ set pll_ctrl [expr {$pll_ctrl & ~0x0010}]
mww $pll_ctrl_addr $pll_ctrl
- # 9 - optional: write prediv, postdiv, and pllm
- # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
- mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
+ # 9 - optional: write prediv, postdiv, and pllm
+ # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
+ mww [expr {$pll_addr + 0x0110}] [expr {($mult - 1) & 0xff}]
if { [dict exists $config prediv] } {
set div [dict get $config prediv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0114] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0114}] $div
}
if { [dict exists $config postdiv] } {
set div [dict get $config postdiv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0128] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0128}] $div
}
- # 10 - optional: set plldiv1, plldiv2, ...
+ # 10 - optional: set plldiv1, plldiv2, ...
# NOTE: this assumes some registers have their just-reset values:
# - PLLSTAT.GOSTAT is clear when we enter
# - ALNCTL has everything set
set go 0
if { [dict exists $config div1] } {
set div [dict get $config div1]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0118] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0118}] $div
set go 1
}
if { [dict exists $config div2] } {
set div [dict get $config div2]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x011c] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x011c}] $div
set go 1
}
if { [dict exists $config div3] } {
set div [dict get $config div3]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0120] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0120}] $div
set go 1
}
if { [dict exists $config div4] } {
set div [dict get $config div4]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0160] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0160}] $div
set go 1
}
if { [dict exists $config div5] } {
set div [dict get $config div5]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0164] $div
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0164}] $div
set go 1
}
if {$go != 0} {
# write pllcmd.GO; poll pllstat.GO
- mww [expr $pll_addr + 0x0138] 0x01
- set pllstat [expr $pll_addr + 0x013c]
- while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
+ mww [expr {$pll_addr + 0x0138}] 0x01
+ set pllstat [expr {$pll_addr + 0x013c}]
+ while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
}
- mww [expr $pll_addr + 0x0138] 0x00
+ mww [expr {$pll_addr + 0x0138}] 0x00
# 11 - wait at least 5 usec for reset to finish
# (assume covered by overheads including JTAG messaging)
# 12 - clear PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl & ~0x0008]
+ set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
mww $pll_ctrl_addr $pll_ctrl
# 13 - wait at least 8000 refclk cycles for PLL to lock
sleep 3
# 14 - set PLLEN (bit 0) ... leave bypass mode
- set pll_ctrl [expr $pll_ctrl | 0x0001]
+ set pll_ctrl [expr {$pll_ctrl | 0x0001}]
+ mww $pll_ctrl_addr $pll_ctrl
+}
+
+# PLL version 0x03: tested on dm365
+proc pll_v03_setup {pll_addr mult config} {
+ set pll_ctrl_addr [expr {$pll_addr + 0x100}]
+ set pll_secctrl_addr [expr {$pll_addr + 0x108}]
+ set pll_ctrl [mrw $pll_ctrl_addr]
+
+ # 1 - power up the PLL
+ set pll_ctrl [expr {$pll_ctrl & ~0x0002}]
+ mww $pll_ctrl_addr $pll_ctrl
+
+ # 2 - clear PLLENSRC (bit 5)
+ set pll_ctrl [expr {$pll_ctrl & ~0x0020}]
+ mww $pll_ctrl_addr $pll_ctrl
+
+ # 2 - clear PLLEN (bit 0) ... enter bypass mode
+ set pll_ctrl [expr {$pll_ctrl & ~0x0001}]
+ mww $pll_ctrl_addr $pll_ctrl
+
+ # 3 - wait at least 4 refclk cycles
+ sleep 1
+
+ # 4 - set PLLRST (bit 3)
+ set pll_ctrl [expr {$pll_ctrl | 0x0008}]
+ mww $pll_ctrl_addr $pll_ctrl
+
+ # 5 - wait at least 5 usec
+ sleep 1
+
+ # 6 - clear PLLRST (bit 3)
+ set pll_ctrl [expr {$pll_ctrl & ~0x0008}]
+ mww $pll_ctrl_addr $pll_ctrl
+
+ # 9 - optional: write prediv, postdiv, and pllm
+ mww [expr {$pll_addr + 0x0110}] [expr {($mult / 2) & 0x1ff}]
+ if { [dict exists $config prediv] } {
+ set div [dict get $config prediv]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0114}] $div
+ }
+ if { [dict exists $config postdiv] } {
+ set div [dict get $config postdiv]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0128}] $div
+ }
+
+ # 10 - write start sequence to PLLSECCTL
+ mww $pll_secctrl_addr 0x00470000
+ mww $pll_secctrl_addr 0x00460000
+ mww $pll_secctrl_addr 0x00400000
+ mww $pll_secctrl_addr 0x00410000
+
+ # 11 - optional: set plldiv1, plldiv2, ...
+ # NOTE: this assumes some registers have their just-reset values:
+ # - PLLSTAT.GOSTAT is clear when we enter
+ set aln 0
+ if { [dict exists $config div1] } {
+ set div [dict get $config div1]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0118}] $div
+ set aln [expr {$aln | 0x1}]
+ } else {
+ mww [expr {$pll_addr + 0x0118}] 0
+ }
+ if { [dict exists $config div2] } {
+ set div [dict get $config div2]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x011c}] $div
+ set aln [expr {$aln | 0x2}]
+ } else {
+ mww [expr {$pll_addr + 0x011c}] 0
+ }
+ if { [dict exists $config div3] } {
+ set div [dict get $config div3]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0120}] $div
+ set aln [expr {$aln | 0x4}]
+ } else {
+ mww [expr {$pll_addr + 0x0120}] 0
+ }
+ if { [dict exists $config oscdiv] } {
+ set div [dict get $config oscdiv]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0124}] $div
+ } else {
+ mww [expr {$pll_addr + 0x0124}] 0
+ }
+ if { [dict exists $config div4] } {
+ set div [dict get $config div4]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0160}] $div
+ set aln [expr {$aln | 0x8}]
+ } else {
+ mww [expr {$pll_addr + 0x0160}] 0
+ }
+ if { [dict exists $config div5] } {
+ set div [dict get $config div5]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0164}] $div
+ set aln [expr {$aln | 0x10}]
+ } else {
+ mww [expr {$pll_addr + 0x0164}] 0
+ }
+ if { [dict exists $config div6] } {
+ set div [dict get $config div6]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0168}] $div
+ set aln [expr {$aln | 0x20}]
+ } else {
+ mww [expr {$pll_addr + 0x0168}] 0
+ }
+ if { [dict exists $config div7] } {
+ set div [dict get $config div7]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x016c}] $div
+ set aln [expr {$aln | 0x40}]
+ } else {
+ mww [expr {$pll_addr + 0x016c}] 0
+ }
+ if { [dict exists $config div8] } {
+ set div [dict get $config div8]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0170}] $div
+ set aln [expr {$aln | 0x80}]
+ } else {
+ mww [expr {$pll_addr + 0x0170}] 0
+ }
+ if { [dict exists $config div9] } {
+ set div [dict get $config div9]
+ set div [expr {0x8000 | ($div - 1)}]
+ mww [expr {$pll_addr + 0x0174}] $div
+ set aln [expr {$aln | 0x100}]
+ } else {
+ mww [expr {$pll_addr + 0x0174}] 0
+ }
+ if {$aln != 0} {
+ # clear pllcmd.GO
+ mww [expr {$pll_addr + 0x0138}] 0x00
+ # write alignment flags
+ mww [expr {$pll_addr + 0x0140}] $aln
+ # write pllcmd.GO; poll pllstat.GO
+ mww [expr {$pll_addr + 0x0138}] 0x01
+ set pllstat [expr {$pll_addr + 0x013c}]
+ while {[expr {[mrw $pllstat] & 0x01}] != 0} { sleep 1 }
+ }
+ mww [expr {$pll_addr + 0x0138}] 0x00
+ set addr [dict get $config ctladdr]
+ while {[expr {[mrw $addr] & 0x0e000000}] != 0x0e000000} { sleep 1 }
+
+ # 12 - set PLLEN (bit 0) ... leave bypass mode
+ set pll_ctrl [expr {$pll_ctrl | 0x0001}]
mww $pll_ctrl_addr $pll_ctrl
}
-# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
+# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
# modules can be enabled.
# prepare a non-DSP module to be enabled; finish with psc_go
proc psc_enable {module} {
set psc_addr 0x01c41000
# write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
+ mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x03 0x1f
}
# prepare a non-DSP module to be reset; finish with psc_go
proc psc_reset {module} {
set psc_addr 0x01c41000
# write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
+ mmw [expr {$psc_addr + 0x0a00 + (4 * $module)}] 0x01 0x1f
}
# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
proc psc_go {} {
set psc_addr 0x01c41000
- set ptstat_addr [expr $psc_addr + 0x0128]
+ set ptstat_addr [expr {$psc_addr + 0x0128}]
# just in case PTSTAT.go isn't clear
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
+ while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
# write PTCMD.go ... ignoring any DSP power domain
- mww [expr $psc_addr + 0x0120] 1
+ mww [expr {$psc_addr + 0x0120}] 1
# wait for PTSTAT.go to clear (again ignoring DSP power domain)
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
+ while { [expr {[mrw $ptstat_addr] & 0x01}] != 0 } { sleep 1 }
}
#
#
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+ mww phys [expr {$timer2_phys + 0x28}] 0x00004000
#
# Part II -- in case watchdog hasn't been set up
#
# TCR: disable, force internal clock source
- arm926ejs mww_phys [expr $timer2_phys + 0x20] 0
+ mww phys [expr {$timer2_phys + 0x20}] 0
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
- arm926ejs mww_phys [expr $timer2_phys + 0x24] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x24] 0x110b
+ mww phys [expr {$timer2_phys + 0x24}] 0
+ mww phys [expr {$timer2_phys + 0x24}] 0x110b
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
# so watchdog triggers ASAP
- arm926ejs mww_phys [expr $timer2_phys + 0x10] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x14] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x18] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x1c] 0
+ mww phys [expr {$timer2_phys + 0x10}] 0
+ mww phys [expr {$timer2_phys + 0x14}] 0
+ mww phys [expr {$timer2_phys + 0x18}] 0
+ mww phys [expr {$timer2_phys + 0x1c}] 0
# WDTCR: put into pre-active state, then active
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xa5c64000
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xda7e4000
+ mww phys [expr {$timer2_phys + 0x28}] 0xa5c64000
+ mww phys [expr {$timer2_phys + 0x28}] 0xda7e4000
#
# Part III -- it's ready to rumble
#
# WDTCR: write invalid WDKEY to trigger reset
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+ mww phys [expr {$timer2_phys + 0x28}] 0x00004000
}
projects / fw / openocd / blobdiff