+# SPDX-License-Identifier: GPL-2.0-or-later
proc helpC100 {} {
echo "List of useful functions for C100 processor:"
echo "10) showArmClk: will show current config registers for Arm Bus Clock"
echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
echo "12) ooma_board_detect: will show which version of Telo you have"
- echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
+ echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured"
echo "14) showDDR2: will show DDR2 config registers"
- echo "15) showWatchdog: will show current regster config for watchdog"
+ echo "15) showWatchdog: will show current register config for watchdog"
echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
echo "17) bootNOR: will boot Telo from NOR"
- echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
+ echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured"
echo "19) putcUART0: will print a character on UART0"
echo "20) putsUART0: will print a string on UART0"
- echo "21) trainDDR2: will run DDR2 training program"
- echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
+ echo "21) trainDDR2: will run DDR2 training program"
+ echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin"
}
source [find mem_helper.tcl]
# read a 64-bit register (memory mapped)
proc mr64bit {reg} {
- set value ""
- mem2array value 32 $reg 2
- return $value
+ return [read_memory $reg 32 2]
}
# write a 64-bit register (memory mapped)
proc mw64bit {reg value} {
- set high [expr $value >> 32]
- set low [expr $value & 0xffffffff]
+ set high [expr {$value >> 32}]
+ set low [expr {$value & 0xffffffff}]
#echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
mww $reg $low
- mww [expr $reg+4] $high
+ mww [expr {$reg+4}] $high
}
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
- mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
+ set value [read_memory $CLKCORE_AHB_CLK_CNTRL 32 1]
# see if the PLL is in bypass mode
- set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
+ set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
- echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
+ echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
- set x [expr ($value(0) & 0x0001F0000) >> 16]
+ set x [expr {($value & 0x0001F0000) >> 16}]
echo [format "x: %d" $x]
- set y [expr ($value(0) & 0x00000007F)]
+ set y [expr {($value & 0x00000007F)}]
echo [format "y: %d" $y]
- set w [expr ($value(0) & 0x000000300) >> 8]
+ set w [expr {($value & 0x000000300) >> 8}]
echo [format "w: %d" $w]
- echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
+ echo [format "Amba PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
}
set x [config x_amba]
set y [config y_amba]
- echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
+ echo [format "Setting Amba PLL to lock to %d MHz" [expr {$CONFIG_SYS_HZ_CLOCK/1000000}]]
#echo [format "setupAmbaClk: w= %d" $w]
#echo [format "setupAmbaClk: x= %d" $x]
#echo [format "setupAmbaClk: y= %d" $y]
sleep 1
# set X, W and X
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
- mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
+ mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
- echo "Wating for Amba PLL to lock"
- while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
+ echo "Waiting for Amba PLL to lock"
+ while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
- mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
+ set value [read_memory $CLKCORE_ARM_CLK_CNTRL 32 1]
# see if the PLL is in bypass mode
- set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
+ set bypass [expr {($value & $PLL_CLK_BYPASS) >> 24}]
echo [format "PLL bypass bit: %d" $bypass]
if {$bypass == 1} {
- echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
+ echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr {$CFG_REFCLKFREQ/1000000}]]
} else {
# nope, extract x,y,w and compute the PLL output freq.
- set x [expr ($value(0) & 0x0001F0000) >> 16]
+ set x [expr {($value & 0x0001F0000) >> 16}]
echo [format "x: %d" $x]
- set y [expr ($value(0) & 0x00000007F)]
+ set y [expr {($value & 0x00000007F)}]
echo [format "y: %d" $y]
- set w [expr ($value(0) & 0x000000300) >> 8]
+ set w [expr {($value & 0x000000300) >> 8}]
echo [format "w: %d" $w]
- echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
+ echo [format "Arm PLL Clk: %d (MHz)" [expr {($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000}]]
}
}
set x [config x_arm]
set y [config y_arm]
- echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
+ echo [format "Setting Arm PLL to lock to %d MHz" [expr {$CFG_ARM_CLOCK/1000000}]]
#echo [format "setupArmClk: w= %d" $w]
#echo [format "setupArmaClk: x= %d" $x]
#echo [format "setupArmaClk: y= %d" $y]
sleep 1
# set X, W and X
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
- mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
+ mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
- echo "Wating for Amba PLL to lock"
- while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
+ echo "Waiting for Amba PLL to lock"
+ while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
# and not reset.
mmw $BLOCK_RESET_REG 0x0 $DDR_RST
- set M [expr 1024 * 1024]
- set DDR_SZ_1024M [expr 1024 * $M]
- set DDR_SZ_256M [expr 256 * $M]
- set DDR_SZ_128M [expr 128 * $M]
- set DDR_SZ_64M [expr 64 * $M]
+ set M [expr {1024 * 1024}]
+ set DDR_SZ_1024M [expr {1024 * $M}]
+ set DDR_SZ_256M [expr {256 * $M}]
+ set DDR_SZ_128M [expr {128 * $M}]
+ set DDR_SZ_64M [expr {64 * $M}]
# ooma_board_detect returns DDR2 memory size
set tmp [ooma_board_detect]
if {$tmp == "128M"} {
}
# Memory setup register
- mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
- # disbale ROM remap
+ mww $MEMORY_MAX_ADDR [expr {($ddr_size - 1) + $MEMORY_BASE_ADDR}]
+ # disable ROM remap
mww $MEMORY_CR 0x0
# Take DDR controller out of reset
mmw $BLOCK_RESET_REG $DDR_RST 0x0
# APB init
# // Setting APB Bus Wait states to 1, set post write
# (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
- mww [expr $APB_ACCESS_WS_REG] 0x40
+ mww $APB_ACCESS_WS_REG 0x40
# AHB init
# // enable all 6 masters for ARAM
- mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
+ mmw $ASA_ARAM_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
# // enable all 6 masters for EBUS
- mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
+ mmw $ASA_EBUS_TC_CR_REG [expr {$ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN}] 0x0
# ARAM init
# // disable pipeline mode in ARAM
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
# allow the counter to count to high value before triggering
- # this is because regsiter writes are slow over JTAG and
+ # this is because register writes are slow over JTAG and
# I don't want to miss the high_bound==curr_count condition
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
adapter speed 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
- echo -n "Wating for watchdog to trigger..."
+ echo -n "Waiting for watchdog to trigger..."
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
# echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
# sleep 1
projects / fw / openocd / blobdiff