# show the value for the param. with label
proc showconfig {label} {
- puts [format "0x%x" [dict get [configC100] $label ]]
+ echo [format "0x%x" [dict get [configC100] $label ]]
}
# Telo board config
}
+# This should be called for reset init event handler
+proc setupTelo {} {
+
+ # setup GPIO used as control signals for C100
+ setupGPIO
+ # This will allow acces to lower 8MB or NOR
+ lowGPIO5
+ # setup NOR size,timing,etc.
+ setupNOR
+ # setup internals + PLL + DDR2
+ initC100
+}
+
+
proc setupNOR {} {
- puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
+ echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
resume
}
proc setupGPIO {} {
- puts "Setting up GPIO block for Telo"
+ echo "Setting up GPIO block for Telo"
# This is current setup for Telo (see sch. for details):
#GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
#GPIO1 irq line for FXS-FXO
}
proc highGPIO5 {} {
- puts "GPIO5 high"
+ echo "GPIO5 high"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=1
mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
}
proc lowGPIO5 {} {
- puts "GPIO5 low"
+ echo "GPIO5 low"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=0
mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
return $boardID
}
+
# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
proc ooma_board_detect {} {
# read the current value of the BOOTSRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
- puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
+ echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
# extract the GPBP bits
set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
# display board ID
- puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+ echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+ # show it on serial console
+ putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
# return the ddr2 size, used to configure DDR2 on a given board.
return [dict get [boardID $gpbt] $gpbt ddr2size]
}
proc configureDDR2regs_256M {} {
- puts "ConfigureDDR2regs_256M TBD"
+
+ set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
+ set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
+ set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
+ set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
+ set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
+ set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
+ set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
+ set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
+ set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
+ set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
+ set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
+ set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
+ set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
+ set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
+ set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
+ set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
+ set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
+ set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
+ set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
+ set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
+ set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
+
+ set DENALI_CTL_02_VAL 0x0100000000010100
+ set DENALI_CTL_11_VAL 0x433a32164a560a00
+
+ mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
+ # 01_DATA mod [40]=1, enable BA2
+ mw64bit $DENALI_CTL_01_DATA 0x0100010100000001
+ mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
+ mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
+ mw64bit $DENALI_CTL_04_DATA 0x0000010100000001
+ mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
+ mw64bit $DENALI_CTL_06_DATA 0x060a020200020202
+ mw64bit $DENALI_CTL_07_DATA 0x0000000300000206
+ mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209
+ mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a
+ mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18
+ # 11_DATA mod [39-32]=16,more refresh
+ mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
+ mw64bit $DENALI_CTL_12_DATA 0x0000000000000800
+ mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
+ mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
+ mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000
+ mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000
+ mw64bit $DENALI_CTL_17_DATA 0x0000000000000000
+ mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
+ mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600
+ mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8
+
+ set wr_dqs_shift 0x40
+ # start DDRC
+ mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
+ # wait int_status[2] (DRAM init complete)
+ echo -n "Waiting for DDR2 controller to init..."
+ set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+ while { [expr $tmp & 0x040000] == 0 } {
+ sleep 1
+ set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+ }
+ echo "done."
+
+ # do ddr2 training sequence
+ # TBD (for now, if you need it, run trainDDR command)
}
# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
# start DDRC
mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
# wait int_status[2] (DRAM init complete)
- puts -nonewline "Waiting for DDR2 controller to init..."
+ echo -n "Waiting for DDR2 controller to init..."
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
while { [expr $tmp & 0x040000] == 0 } {
sleep 1
set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
}
- mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
- puts "done."
+ # This is not necessary
+ #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
+ echo "done."
# do ddr2 training sequence
# TBD (for now, if you need it, run trainDDR command)
resume
}
-proc flashUBOOT {} {
+proc flashUBOOT {file} {
# this will update uboot on NOR partition
set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
# make sure we are accessing the lower part of NOR
lowGPIO5
flash probe 0
- puts "Erasing sectors 0-3 for uboot"
+ echo "Erasing sectors 0-3 for uboot"
+ putsUART0 "Erasing sectors 0-3 for uboot\n"
flash erase_sector 0 0 3
- puts "Programming u-boot, takes about 4-5 min for 256kb"
- flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
+ echo "Programming u-boot"
+ putsUART0 "Programming u-boot..."
+ arm11 memwrite burst enable
+ flash write_image $file $EXP_CS0_BASEADDR
+ arm11 memwrite burst disable
+ putsUART0 "done.\n"
+ putsUART0 "Rebooting, please wait!\n"
+ reboot
}
\ No newline at end of file
projects / fw / openocd / blobdiff