+# SPDX-License-Identifier: GPL-2.0-or-later
-# board(-config) specfic parameters file.
+# board(-config) specific parameters file.
# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
proc config {label} {
# show the value for the param. with label
proc showconfig {label} {
- puts [format "0x%x" [dict get [configC100] $label ]]
+ echo [format "0x%x" [dict get [configC100] $label ]]
}
# Telo board config
dict set configC100 w_amba 1
dict set configC100 x_amba 1
# y = amba_clk * (w+1)*(x+1)*2/xtal_clk
- dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
+ dict set configC100 y_amba [expr {[dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
# Arm Clk 450MHz, must be a multiple of 25 MHz
dict set configC100 CFG_ARM_CLOCK 450000000
dict set configC100 w_arm 0
dict set configC100 x_arm 1
# y = arm_clk * (w+1)*(x+1)*2/xtal_clk
- dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
+ dict set configC100 y_arm [expr {[dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]} ]
}
# setup GPIO used as control signals for C100
setupGPIO
- # This will allow acces to lower 8MB or NOR
+ # This will allow access to lower 8MB or NOR
lowGPIO5
# setup NOR size,timing,etc.
setupNOR
proc setupNOR {} {
- puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
+ echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
# this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
set EX_CSEN_REG [regs EX_CSEN_REG ]
set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
#mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
- # everthing else is OK with default
+ # everything else is OK with default
}
proc bootNOR {} {
resume
}
proc setupGPIO {} {
- puts "Setting up GPIO block for Telo"
+ echo "Setting up GPIO block for Telo"
# This is current setup for Telo (see sch. for details):
#GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
#GPIO1 irq line for FXS-FXO
set GPIO_OE_REG [regs GPIO_OE_REG]
# set GPIO29=GPIO17=1, GPIO5=0
- mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
+ mww $GPIO_OUTPUT_REG [expr {1<<29 | 1<<17}]
# enable [as output] GPIO29,GPIO17,GPIO5
- mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5]
+ mww $GPIO_OE_REG [expr {1<<29 | 1<<17 | 1<<5}]
}
proc highGPIO5 {} {
- puts "GPIO5 high"
+ echo "GPIO5 high"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=1
- mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
+ mmw $GPIO_OUTPUT_REG [expr {1 << 5}] 0x0
}
proc lowGPIO5 {} {
- puts "GPIO5 low"
+ echo "GPIO5 low"
set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
# set GPIO5=0
- mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
+ mmw $GPIO_OUTPUT_REG 0x0 [expr {1 << 5}]
}
proc boardID {id} {
proc ooma_board_detect {} {
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
- # read the current value of the BOOTSRAP pins
+ # read the current value of the BOOTSTRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
- puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
+ echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
# extract the GPBP bits
- set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
+ set gpbt [expr {($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3}]
# display board ID
- puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+ echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
# show it on serial console
putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
# return the ddr2 size, used to configure DDR2 on a given board.
set wr_dqs_shift 0x40
# start DDRC
- mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
+ mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
# wait int_status[2] (DRAM init complete)
- puts -nonewline "Waiting for DDR2 controller to init..."
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- while { [expr $tmp & 0x040000] == 0 } {
+ echo -n "Waiting for DDR2 controller to init..."
+ set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+ while { [expr {$tmp & 0x040000}] == 0 } {
sleep 1
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+ set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
}
- puts "done."
+ echo "done."
# do ddr2 training sequence
# TBD (for now, if you need it, run trainDDR command)
set wr_dqs_shift 0x40
# start DDRC
- mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
+ mw64bit $DENALI_CTL_02_DATA [expr {$DENALI_CTL_02_VAL | (1 << 32)}]
# wait int_status[2] (DRAM init complete)
- puts -nonewline "Waiting for DDR2 controller to init..."
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- while { [expr $tmp & 0x040000] == 0 } {
+ echo -n "Waiting for DDR2 controller to init..."
+ set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
+ while { [expr {$tmp & 0x040000}] == 0 } {
sleep 1
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+ set tmp [mrw [expr {$DENALI_CTL_08_DATA + 4}]]
}
# This is not necessary
- #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
- puts "done."
+ #mw64bit $DENALI_CTL_11_DATA [expr {($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40)} ]
+ echo "done."
# do ddr2 training sequence
# TBD (for now, if you need it, run trainDDR command)
# Enable Divisor Latch access
mmw $UART0_LCR $LCR_DLAB 0x0
# set the divisor to $tmp
- mww $UART0_DLL [expr $tmp & 0xff]
- mww $UART0_DLH [expr $tmp >> 8]
+ mww $UART0_DLL [expr {$tmp & 0xff}]
+ mww $UART0_DLH [expr {$tmp >> 8}]
# Disable Divisor Latch access
mmw $UART0_LCR 0x0 $LCR_DLAB
# set the UART to 8N1
- mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
+ mmw $UART0_LCR [expr {$LCR_ONE_STOP | $LCR_CHAR_LEN_8} ] 0x0
# reset FIFO
- mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
+ mmw $UART0_IIR [expr {$FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN} ] 0x0
# enable FFUART
mww $UART0_IER $IER_UUE
}
# convert the 'char' to digit
set tmp [ scan $char %c ]
# /* wait for room in the tx FIFO on FFUART */
- while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
+ while {[expr {[mrw $UART0_LSR] & $LSR_TEMT}] == 0} { sleep 1 }
mww $UART0_THR $tmp
if { $char == "\n" } { putcUART0 \r }
}
set len [string length $str]
while { $index < $len } {
putcUART0 [string index $str $index]
- set index [expr $index + 1]
+ set index [expr {$index + 1}]
}
}
# make sure we are accessing the lower part of NOR
lowGPIO5
flash probe 0
- puts "Erasing sectors 0-3 for uboot"
+ echo "Erasing sectors 0-3 for uboot"
putsUART0 "Erasing sectors 0-3 for uboot\n"
flash erase_sector 0 0 3
- puts "Programming u-boot"
+ echo "Programming u-boot"
putsUART0 "Programming u-boot..."
arm11 memwrite burst enable
flash write_image $file $EXP_CS0_BASEADDR
putsUART0 "done.\n"
putsUART0 "Rebooting, please wait!\n"
reboot
-}
\ No newline at end of file
+}
projects / fw / openocd / blobdiff