flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / target / c100.cfg

diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg
index ceb8de38f313bbcbf2ed8d9436f16080859da6e7..c268ba3ba20b6d6d54a8171a8dd8224fbcbe7aa5 100644 (file)
--- a/tcl/target/c100.cfg
+++ b/tcl/target/c100.cfg
@@ -1,30 +1,31 @@
-# c100 config
-#
-#jtag_nsrst_delay 5000
-#jtag_ntrst_delay 3000
-#reset_config none
-reset_config trst_and_srst separate
-#reset_config srst_only srst_pulls_trst
+# SPDX-License-Identifier: GPL-2.0-or-later
 
-if { [info exists CHIPNAME] } {        
-   set  _CHIPNAME $CHIPNAME    
-} else {        
-   set  _CHIPNAME c100
+# c100 config.
+# This is ARM1136 dual core
+# this script only configures one core (that is used to run Linux)
+
+# assume no PLL lock, start slowly
+adapter speed 100
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME c100
 }
 
-if { [info exists ENDIAN] } {  
-   set  _ENDIAN $ENDIAN    
-} else {        
-   set  _ENDIAN little
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x27b3645b
 }
 
-if { [info exists DSPTAPID ] } {
+if { [info exists DSPTAPID] } {
    set _DSPTAPID $DSPTAPID
 } else {
    set _DSPTAPID 0x27b3645b
@@ -36,30 +37,8 @@ jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_D
 # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # C100's ARAM 64k SRAM
 $_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
-
-
-proc power_restore {} { puts "Sensed power restore. No action." } 
-proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
-
-
-# issue telnet: reset init
-# issue gdb: monitor reset init
-$_TARGETNAME configure -event reset-init {
-       # Force target into ARM state.
-#      soft_reset_halt # not implemented on ARM11
-       puts "Halting C100.CPU"
-       halt
-}
-
-$_TARGETNAME configure -event reset-deassert-post {
-       # Force target into ARM state.
-#      soft_reset_halt # not implemented on ARM11
-       puts "Detected SRSRT asserted on C100.CPU"
-       
-}
-# Valid events: old-gdb_program_config, old-pre_resume, early-halted, halted, resumed, resume-start, resume-end, gdb-start, gdb-end, reset-start, reset-assert-pre, reset-assert-post, reset-deassert-pre, reset-deassert-post, reset-halt-pre, reset-halt-post, reset-wait-pre, reset-wait-post, reset-init, reset-end, examine-start, examine-end, debug-halted, debug-resumed, gdb-attach, gdb-detach, gdb-flash-write-start, gdb-flash-write-end, gdb-flash-erase-start, gdb-flash-erase-end, resume-start, resume-ok, or resume-end