# This limit is most probably imposed by incorrectly handled SWD WAIT
# on some SWD adapters.
-adapter_khz 400
+adapter speed 400
# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
# without problem at maximal clock speed. Atmel recommends
# adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
+# adapter speed 5000
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to