flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / target / at91sam7sx.cfg

diff --git a/tcl/target/at91sam7sx.cfg b/tcl/target/at91sam7sx.cfg
index 516a09c7e3987c2f3aecf16b249ffa580c790716..fee4e9ae4042dc0f686313aa356df2fe35654c65 100644 (file)
--- a/tcl/target/at91sam7sx.cfg
+++ b/tcl/target/at91sam7sx.cfg
@@ -1,19 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config srst_only srst_pulls_trst
 
-if { [info exists CHIPNAME] } {        
-   set  _CHIPNAME $CHIPNAME    
-} else {        
-   set  _CHIPNAME at91sam7s
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at91sam7s
 }
 
-if { [info exists ENDIAN] } {  
-   set  _ENDIAN $ENDIAN    
-} else {        
-   set  _ENDIAN little
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
    set _CPUTAPID 0x3f0f0f0f
@@ -21,35 +23,33 @@ if { [info exists CPUTAPID ] } {
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
 
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init { 
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -event reset-init {
         soft_reset_halt
         # RSTC_CR : Reset peripherals
         mww 0xfffffd00 0xa5000004
         # disable watchdog
-       mww 0xfffffd44 0x00008000       
+       mww 0xfffffd44 0x00008000
        # enable user reset
-       mww 0xfffffd08 0xa5000001       
+       mww 0xfffffd08 0xa5000001
        # CKGR_MOR : enable the main oscillator
-       mww 0xfffffc20 0x00000601       
+       mww 0xfffffc20 0x00000601
        sleep 10
        # CKGR_PLLR: 96.1097 MHz
-       mww 0xfffffc2c 0x00481c0e       
+       mww 0xfffffc2c 0x00481c0e
        sleep 10
        # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-       mww 0xfffffc30 0x00000007       
+       mww 0xfffffc30 0x00000007
        sleep 10
        # MC_FMR: flash mode (FWS=1,FMCN=73)
-       mww 0xffffff60 0x00490100       
-       sleep 100        
+       mww 0xffffff60 0x00490100
+       sleep 100
 }
 
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432