tcl/target/ti_k3: Add J721S2 SoC

[fw/openocd] / tcl / target / at91sam4lXX.cfg

diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 46c38aef2dd998d566a8a8f86e6f1cc7c5d843ec..b73babcbb11f04fcaf30f5f3153f76b52450ad0c 100644 (file)
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -1,4 +1,4 @@
-# script for ATMEL sam4l, a CORTEX-M4 chip
+# script for ATMEL sam4l, a Cortex-M4 chip
 #
 
 source [find target/at91sam4XXX.cfg]
@@ -21,7 +21,7 @@ reset_config srst_gates_jtag
 # Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
 # Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
 # but your mileage may vary.
-adapter_khz 50
+adapter speed 50
 
 # System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
+adapter srst delay 0