tcl/target: add SPDX tag

[fw/openocd] / tcl / target / at91sam4lXX.cfg

diff --git a/tcl/target/at91sam4lXX.cfg b/tcl/target/at91sam4lXX.cfg
index 77ff98a8c95eac2dc038d654683d1602e879a8ba..0910e3080a8b24e08a062a34f65b30c90493910b 100644 (file)
--- a/tcl/target/at91sam4lXX.cfg
+++ b/tcl/target/at91sam4lXX.cfg
@@ -1,4 +1,6 @@
-# script for ATMEL sam4l, a CORTEX-M4 chip
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for ATMEL sam4l, a Cortex-M4 chip
 #
 
 source [find target/at91sam4XXX.cfg]
@@ -6,6 +8,22 @@ source [find target/at91sam4XXX.cfg]
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
 
-# if srst is not fitted use VECTRESET to perform a soft reset
-# this will only reset the core, not the peripherals
-cortex_m reset_config vectreset
+# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
+# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
+#
+# smap_reset_deassert configures whether we want to run or halt out of reset,
+# then instruct the SMAP to let us out of reset.
+$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"
+
+# SRST (wired to RESET_N) resets debug circuitry
+# srst_pulls_trst is not configured here to avoid an error raised in reset halt
+reset_config srst_gates_jtag
+
+# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
+# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
+# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
+# but your mileage may vary.
+adapter speed 50
+
+# System RC oscillator RCSYS starts in 3 cycles
+adapter srst delay 0