mips: optimize write code for speed

[fw/openocd] / tcl / target / at91sam3XXX.cfg

diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg
index a13e39901368f74464790ee7f17c559d86bf0d60..b90e3f0157c93fcbeb1d9b9e78452f7eba9e907d 100644 (file)
--- a/tcl/target/at91sam3XXX.cfg
+++ b/tcl/target/at91sam3XXX.cfg
@@ -16,7 +16,14 @@
 # at91sam3s1c
 # at91sam3s1b
 # at91sam3s1a
-
+#
+# at91sam3A4C
+# at91sam3A8C
+# at91sam3X4C
+# at91sam3X4E
+# at91sam3X8C
+# at91sam3X8E
+# at91sam3X8H
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -29,6 +36,18 @@ if { [info exists ENDIAN] } {
    set _ENDIAN little
 }
 
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+
+adapter_khz 500
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
@@ -47,3 +66,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar
 $_TARGETNAME configure -event gdb-flash-erase-start {
     halt
 }
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq