tcl/target: add SPDX tag

[fw/openocd] / tcl / target / ar71xx.cfg

diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg
index 3ac61d94638c855382f804bb6f2ee9f4310870d6..792b68f3ab7137b3ccb89bf0df9282664b44156e 100644 (file)
--- a/tcl/target/ar71xx.cfg
+++ b/tcl/target/ar71xx.cfg
@@ -1,7 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Atheros AR71xx MIPS 24Kc SoC.
 # tested on PB44 refererence board
 
-adapter_nsrst_delay 100
+adapter srst delay 100
 jtag_ntrst_delay 100
 
 reset_config trst_and_srst
@@ -10,10 +12,10 @@ set CHIPNAME ar71xx
 
 jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
 
-set TARGETNAME $CHIPNAME.cpu
-target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
+set _TARGETNAME $CHIPNAME.cpu
+target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
 
-$TARGETNAME configure -event reset-halt-post {
+$_TARGETNAME configure -event reset-halt-post {
        #setup PLL to lowest common denominator 300/300/150 setting
        mww 0xb8050000 0x000f40a3       ;# reset val + CPU:3 DDR:3 AHB:0
        mww 0xb8050000 0x800f40a3       ;# send to PLL
@@ -22,7 +24,7 @@ $TARGETNAME configure -event reset-halt-post {
        mww 0xb8050008 3                ;# set reset_switch and clock_switch (resets SoC)
 }
 
-$TARGETNAME configure -event reset-init {
+$_TARGETNAME configure -event reset-init {
        #complete pll initialization
        mww 0xb8050000 0x800f0080       ;# set sw_update bit
        mww 0xb8050008 0                ;# clear reset_switch bit
@@ -50,8 +52,7 @@ $TARGETNAME configure -event reset-init {
 }
 
 # setup working area somewhere in RAM
-$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
+$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
 
 # serial SPI capable flash
 # flash bank <driver> <base> <size> <chip_width> <bus_width>
-