# Atheros AR71xx MIPS 24Kc SoC.
# tested on PB44 refererence board
-jtag_nsrst_delay 100
+adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
-set TARGETNAME [format "%s.cpu" $CHIPNAME]
+set TARGETNAME $CHIPNAME.cpu
target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
-$TARGETNAME configure -event reset-init {
+$TARGETNAME configure -event reset-halt-post {
#setup PLL to lowest common denominator 300/300/150 setting
mww 0xb8050000 0x000f40a3 # reset val + CPU:3 DDR:3 AHB:0
mww 0xb8050000 0x800f40a3 # send to PLL
#next command will reset for PLL changes to take effect
mww 0xb8050008 3 # set reset_switch and clock_switch (resets SoC)
- reset halt # let openocd know that it is in the reset state
+}
- #initialize_pll
+$TARGETNAME configure -event reset-init {
+ #complete pll initialization
mww 0xb8050000 0x800f0080 # set sw_update bit
mww 0xb8050008 0 # clear reset_switch bit
mww 0xb8050000 0x800f00e8 # clr pwrdwn & bypass
mww 0xb8050008 1 # set clock_switch bit
sleep 1 # wait for lock
-
+
# Setup DDR config and flash mapping
mww 0xb8000000 0xefbc8cd0 # DDR cfg cdl val (rst: 0x5bfc8d0)
mww 0xb8000004 0x8e7156a2 # DDR cfg2 cdl val (rst: 0x80d106a8)
-
+
mww 0xb8000010 8 # force precharge all banks
mww 0xb8000010 1 # force EMRS update cycle
mww 0xb800000c 0 # clr ext. mode register
mww 0xb8000020 0
mww 0xb8000024 0
mww 0xb8000028 0
-}
+}
# setup working area somewhere in RAM
$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000