+# SPDX-License-Identifier: GPL-2.0-or-later
+
#
# Copyright (C) 2010-2011 by Karl Kurbjun
# Copyright (C) 2009-2011 by Øyvind Harboe
# Run the adapter at the fastest acceptable speed with the slowest possible
# core clock.
-adapter_khz 10
+adapter speed 10
###############################################################################
# JTAG setup
# The OpenOCD commands are described in the TAP Declaration section
-# http://openocd.sourceforge.net/doc/html/TAP-Declaration.html
+# http://openocd.org/doc/html/TAP-Declaration.html
###############################################################################
# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
# The TAP order should be described from the TDO connection in OpenOCD to the
# TDI pin. The OpenOCD FAQ describes this in more detail:
-# http://openocd.sourceforge.net/doc/html/FAQ.html
+# http://openocd.org/doc/html/FAQ.html
# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
#
# Secondary TAP: DAP is closest to the TDO output
# The TAP enable event also needs to be described
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# These taps are only present in the DM37x series.
###############################################################################
# Target Setup:
# This section is described in the OpenOCD documentation under CPU Configuration
-# http://openocd.sourceforge.net/doc/html/CPU-Configuration.html
+# http://openocd.org/doc/html/CPU-Configuration.html
###############################################################################
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
# Describe the reset assert process for openocd - this is asserted with the
# ICEPick
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
- adapter_khz 1000
+ adapter speed 1000
}
$_TARGETNAME configure -event gdb-attach {
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc amdm37x_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# at this address and this bit.
$target mww phys 0x5401d030 0x00002000
}
-