tcl/target: add SPDX tag

[fw/openocd] / tcl / target / am437x.cfg

diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg
index e0813ca521eabd8ac1d62cd792319e5ee49fc05a..5350927583d20f78c5983d08683e0f632ace2f49 100644 (file)
--- a/tcl/target/am437x.cfg
+++ b/tcl/target/am437x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/icepick.cfg]
 source [find mem_helper.tcl]
 
@@ -512,10 +514,10 @@ proc disable_watchdog { } {
                # Empty body to make sure this executes as fast as possible.
                # We don't want any delays here otherwise romcode might start
                # executing and end up changing state of certain IPs.
-               while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
+               while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
 
                mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
-               while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
+               while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
        }
 }
 
@@ -725,13 +727,13 @@ proc emif_prcm_clk_enable { } {
 proc vtp_enable { } {
        global VTP_CTRL_REG
 
-       set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ]
+       set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
        mww $VTP_CTRL_REG $vtp
 
-       set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ]
+       set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
        mww $VTP_CTRL_REG $vtp
 
-       set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ]
+       set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
        mww $VTP_CTRL_REG $vtp
 
 }
@@ -948,7 +950,7 @@ proc config_ddr3 { SDRAM_CONFIG } {
        emif_prcm_clk_enable
        vtp_enable
 
-       set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ]
+       set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
        mww $CM_DLL_CTRL $dll
        while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
 
@@ -978,7 +980,7 @@ proc config_ddr3 { SDRAM_CONFIG } {
 
        sleep 10
 
-       set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ]
+       set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
        mww $EXT_PHY_CTRL_36            $tmp
        mww $EXT_PHY_CTRL_36_SHDW       $tmp