cfg: add TI am43xx devices

[fw/openocd] / tcl / target / am437x.cfg

diff --git a/tcl/target/am437x.cfg b/tcl/target/am437x.cfg
new file mode 100644 (file)
index 0000000..e9a6606
--- /dev/null
+++ b/tcl/target/am437x.cfg
@@ -0,0 +1,51 @@
+source [find target/icepick.cfg]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME am437x
+}
+
+#
+# M3 DAP
+#
+if { [info exists M3_DAP_TAPID] } {
+       set _M3_DAP_TAPID $M3_DAP_TAPID
+} else {
+       set _M3_DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
+
+#
+# Cortex A9 DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4b6b902f
+}
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
+
+#
+# ICEpick-D (JTAG route controller)
+#
+if { [info exists JRC_TAPID] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b98c02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+#
+# Cortex A9 target
+#
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+
+# SRAM: 64K at 0x4030.0000; use the first 16K
+$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000