flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / target / am335x.cfg

diff --git a/tcl/target/am335x.cfg b/tcl/target/am335x.cfg
index 3ca196b11977a98e52deeb91db2c016afa955213..208ebf5610869b50e598e64c867349832ce213e6 100644 (file)
--- a/tcl/target/am335x.cfg
+++ b/tcl/target/am335x.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 source [find target/icepick.cfg]
 
 if { [info exists CHIPNAME] } {
@@ -12,7 +14,7 @@ if { [info exists CHIPNAME] } {
 if { [info exists DEFAULT_TAPS] } {
        set _DEFAULT_TAPS "$DEFAULT_TAPS"
 } else {
-       set _DEFAULT_TAPS "$_CHIPNAME.dap"
+       set _DEFAULT_TAPS "$_CHIPNAME.tap"
 }
 
 #
@@ -23,8 +25,9 @@ if { [info exists DAP_TAPID] } {
 } else {
        set _DAP_TAPID 0x4b6b902f
 }
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
+jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
+jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
 
 #
 # M3 DAP
@@ -34,8 +37,9 @@ if { [info exists M3_DAP_TAPID] } {
 } else {
        set _M3_DAP_TAPID 0x4b6b902f
 }
-jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
+jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
+jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
+dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
 
 #
 # ICEpick-D (JTAG route controller)
@@ -66,13 +70,13 @@ proc enable_default_taps { taps } {
 # Cortex-M3 target
 #
 set _TARGETNAME_2 $_CHIPNAME.m3
-target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
+target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
 
 #
 # Cortex-A8 target
 #
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
 
 # SRAM: 64K at 0x4030.0000; use the first 16K
 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
@@ -83,8 +87,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
 # FIXME: unify with target/am437x.cfg
 source [find mem_helper.tcl]
 set  WDT1_BASE_ADDR                  0x44e35000
-set  WDT1_W_PEND_WSPR                [expr       $WDT1_BASE_ADDR     +  0x0034]
-set  WDT1_WSPR                       [expr       $WDT1_BASE_ADDR     +  0x0048]
+set  WDT1_W_PEND_WSPR                [expr       {$WDT1_BASE_ADDR     +  0x0034}]
+set  WDT1_WSPR                       [expr       {$WDT1_BASE_ADDR     +  0x0048}]
 proc disable_watchdog { } {
        global WDT1_WSPR
        global WDT1_W_PEND_WSPR
@@ -101,10 +105,10 @@ proc disable_watchdog { } {
                # Empty body to make sure this executes as fast as possible.
                # We don't want any delays here otherwise romcode might start
                # executing and end up changing state of certain IPs.
-               while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
+               while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
 
                mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
-               while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
+               while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
        }
 }
 $_TARGETNAME configure -event reset-end { disable_watchdog }