+# SPDX-License-Identifier: GPL-2.0-or-later
+
#
# Altera cyclone V SoC family, 5Cxxx
#
set _DAP_TAPID 0x4ba00477
}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
# Subsidiary TAP: fpga
#
-# Cortex A9 target
+# Cortex-A9 target
#
# GDB target: Cortex-A9, using DAP, configuring only one core
# core 1 - 0x80112000
# Slow speed to be sure it will work
-jtag_rclk 1000
+adapter speed 1000
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
# A9 core 0
-target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
-$_TARGETNAME1 configure -event reset-start { jtag_rclk 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
-$_TARGETNAME1 configure -event gdb-attach { halt }
# A9 core 1
-#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
+#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
-#$_TARGETNAME2 configure -event reset-start { jtag_rclk 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
-#$_TARGETNAME2 configure -event gdb-attach { halt }
proc cycv_dbginit {target} {
- # General Cortex A8/A9 debug initialisation
- cortex_a8 dbginit
+ # General Cortex-A8/A9 debug initialisation
+ cortex_a dbginit
}