flash/nor/stm32f1x: Add support for GD32E23x

[fw/openocd] / tcl / memory.tcl

diff --git a/tcl/memory.tcl b/tcl/memory.tcl
index c4418fa1bed5ef4dc5659b4588305a96b13f3ccc..8d50ba8531ae50acd323ffa5b10f6a6a6ea0ab21 100644 (file)
--- a/tcl/memory.tcl
+++ b/tcl/memory.tcl
@@ -43,9 +43,9 @@ set RWX_NO_ACCESS     0
 set RWX_X_ONLY        $BIT0
 set RWX_W_ONLY        $BIT1
 set RWX_R_ONLY        $BIT2
-set RWX_RW            [expr $RWX_R_ONLY + $RWX_W_ONLY]
-set RWX_R_X           [expr $RWX_R_ONLY + $RWX_X_ONLY]
-set RWX_RWX           [expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY]
+set RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
+set RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
+set RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
 set UNKNOWN(0,RWX)     $RWX_NO_ACCESS
 
 #     WIDTH       - access width
@@ -54,11 +54,11 @@ set ACCESS_WIDTH_NONE 0
 set ACCESS_WIDTH_8    $BIT0
 set ACCESS_WIDTH_16   $BIT1
 set ACCESS_WIDTH_32   $BIT2
-set ACCESS_WIDTH_ANY  [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32]
+set ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
 set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
 
 proc iswithin { ADDRESS BASE LEN } {
-    return [expr ((($ADDRESS - $BASE) > 0) && (($ADDRESS - $BASE + $LEN) > 0))]
+    return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
 }
 
 proc address_info { ADDRESS } {
@@ -80,7 +80,7 @@ proc address_info { ADDRESS } {
 
 proc memread32 {ADDR} {
     set foo(0) 0
-    if ![ catch { ocd_mem2array foo 32 $ADDR 1  } msg ] {
+    if ![ catch { mem2array foo 32 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memread32: $msg"
@@ -89,7 +89,7 @@ proc memread32 {ADDR} {
 
 proc memread16 {ADDR} {
     set foo(0) 0
-    if ![ catch { ocd_mem2array foo 16 $ADDR 1  } msg ] {
+    if ![ catch { mem2array foo 16 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memread16: $msg"
@@ -98,7 +98,7 @@ proc memread16 {ADDR} {
 
 proc memread8 {ADDR} {
     set foo(0) 0
-    if ![ catch { ocd_mem2array foo 8 $ADDR 1  } msg ] {
+    if ![ catch { mem2array foo 8 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memread8: $msg"
@@ -107,7 +107,7 @@ proc memread8 {ADDR} {
 
 proc memwrite32 {ADDR DATA} {
     set foo(0) $DATA
-    if ![ catch { ocd_array2mem foo 32 $ADDR 1  } msg ] {
+    if ![ catch { array2mem foo 32 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memwrite32: $msg"
@@ -116,7 +116,7 @@ proc memwrite32 {ADDR DATA} {
 
 proc memwrite16 {ADDR DATA} {
     set foo(0) $DATA
-    if ![ catch { ocd_array2mem foo 16 $ADDR 1  } msg ] {
+    if ![ catch { array2mem foo 16 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memwrite16: $msg"
@@ -125,7 +125,61 @@ proc memwrite16 {ADDR DATA} {
 
 proc memwrite8 {ADDR DATA} {
     set foo(0) $DATA
-    if ![ catch { ocd_array2mem foo 8 $ADDR 1  } msg ] {
+    if ![ catch { array2mem foo 8 $ADDR 1  } msg ] {
+       return $foo(0)
+    } else {
+       error "memwrite8: $msg"
+    }
+}
+
+proc memread32_phys {ADDR} {
+    set foo(0) 0
+    if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memread32: $msg"
+    }
+}
+
+proc memread16_phys {ADDR} {
+    set foo(0) 0
+    if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memread16: $msg"
+    }
+}
+
+proc memread8_phys {ADDR} {
+    set foo(0) 0
+    if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memread8: $msg"
+    }
+}
+
+proc memwrite32_phys {ADDR DATA} {
+    set foo(0) $DATA
+    if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memwrite32: $msg"
+    }
+}
+
+proc memwrite16_phys {ADDR DATA} {
+    set foo(0) $DATA
+    if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memwrite16: $msg"
+    }
+}
+
+proc memwrite8_phys {ADDR DATA} {
+    set foo(0) $DATA
+    if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
        return $foo(0)
     } else {
        error "memwrite8: $msg"