tcl: add SPDX tag

[fw/openocd] / tcl / chip / st / stm32 / stm32_rcc.tcl

diff --git a/tcl/chip/st/stm32/stm32_rcc.tcl b/tcl/chip/st/stm32/stm32_rcc.tcl
index 3973ff94194c542707bd78fb950f329ac4adddbc..afa4cbfd6af9d3c90e7a99168dfb544b83b79331 100644 (file)
--- a/tcl/chip/st/stm32/stm32_rcc.tcl
+++ b/tcl/chip/st/stm32/stm32_rcc.tcl
@@ -1,14 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
 
-set RCC_CR            [expr $RCC_BASE + 0x00]
-set RCC_CFGR          [expr $RCC_BASE + 0x04]
-set RCC_CIR           [expr $RCC_BASE + 0x08]
-set RCC_APB2RSTR      [expr $RCC_BASE + 0x0c]
-set RCC_APB1RSTR      [expr $RCC_BASE + 0x10]
-set RCC_AHBENR        [expr $RCC_BASE + 0x14]
-set RCC_APB2ENR       [expr $RCC_BASE + 0x18]
-set RCC_APB1ENR       [expr $RCC_BASE + 0x1c]
-set RCC_BDCR          [expr $RCC_BASE + 0x20]
-set RCC_CSR           [expr $RCC_BASE + 0x24]
+set RCC_CR            [expr {$RCC_BASE + 0x00}]
+set RCC_CFGR          [expr {$RCC_BASE + 0x04}]
+set RCC_CIR           [expr {$RCC_BASE + 0x08}]
+set RCC_APB2RSTR      [expr {$RCC_BASE + 0x0c}]
+set RCC_APB1RSTR      [expr {$RCC_BASE + 0x10}]
+set RCC_AHBENR        [expr {$RCC_BASE + 0x14}]
+set RCC_APB2ENR       [expr {$RCC_BASE + 0x18}]
+set RCC_APB1ENR       [expr {$RCC_BASE + 0x1c}]
+set RCC_BDCR          [expr {$RCC_BASE + 0x20}]
+set RCC_CSR           [expr {$RCC_BASE + 0x24}]
 
 
 proc show_RCC_CR { } {
@@ -16,7 +17,7 @@ proc show_RCC_CR { } {
        error $msg
     }
 
-    show_mmr_bitfield  0  0 $val HSI      { OFF ON } 
+    show_mmr_bitfield  0  0 $val HSI      { OFF ON }
     show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }
     show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }
     show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }
@@ -26,8 +27,8 @@ proc show_RCC_CR { } {
     show_mmr_bitfield 19 19 $val CSSON    { OFF ON }
     show_mmr_bitfield 24 24 $val PLLON    { OFF ON }
     show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }
-}    
-       
+}
+
 proc show_RCC_CFGR { } {
     if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
        error $msg
@@ -47,12 +48,12 @@ proc show_RCC_CFGR { } {
     show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }
 }
 
-    
+
 proc show_RCC_CIR { } {
     if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
        error $msg
     }
- 
+
 }
 
 proc show_RCC_APB2RSTR { } {
@@ -106,7 +107,7 @@ proc show_RCC_APB1RSTR { } {
     set bits(13) xxx
     set bits(12) xxx
     set bits(11) wwdg
-    set bits(10) xxx 
+    set bits(10) xxx
     set bits(9) xxx
     set bits(8) xxx
     set bits(7) xxx
@@ -118,7 +119,7 @@ proc show_RCC_APB1RSTR { } {
     set bits(1) tim3
     set bits(0) tim2
     show_mmr32_bits bits $val
-    
+
 }
 
 proc show_RCC_AHBENR   { } {
@@ -141,7 +142,7 @@ proc show_RCC_AHBENR   { } {
     set bits(18) xxx
     set bits(17) xxx
     set bits(16) xxx
-    set bits(15) xxx  
+    set bits(15) xxx
     set bits(14) xxx
     set bits(13) xxx
     set bits(12) xxx
@@ -180,7 +181,7 @@ proc show_RCC_APB2ENR  { } {
     set bits(18) xxx
     set bits(17) xxx
     set bits(16) xxx
-    set bits(15) adc3  
+    set bits(15) adc3
     set bits(14) usart1
     set bits(13) tim8
     set bits(12) spi1