tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

[fw/openocd] / tcl / chip / st / spear / spear3xx.tcl

diff --git a/tcl/chip/st/spear/spear3xx.tcl b/tcl/chip/st/spear/spear3xx.tcl
index ef38841379501c7bc26188c940cf33875dc01646..86f2a1d2459a736ebe682965b9ab9e279bc77d46 100644 (file)
--- a/tcl/chip/st/spear/spear3xx.tcl
+++ b/tcl/chip/st/spear/spear3xx.tcl
@@ -19,7 +19,7 @@ proc sp3xx_clock_default {} {
        mww 0xfca00014 0x0ffffff8       ;# set pll timeout to minimum (100us ?!?)
 
        # DDRCORE disable to change frequency
-       set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
+       set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
        mww 0xfca8002c $val
        mww 0xfca8002c $val ;# Yes, write twice!
 
@@ -29,7 +29,7 @@ proc sp3xx_clock_default {} {
        mww 0xfca80008 0x00001c0e       ;# enable
        mww 0xfca80008 0x00001c06       ;# strobe
        mww 0xfca80008 0x00001c0e
-       while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
+       while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
 
        # programming PLL2
        mww 0xfca80018 0xa600010c       ;# M=166, P=1, N=12
@@ -37,13 +37,13 @@ proc sp3xx_clock_default {} {
        mww 0xfca80014 0x00001c0e       ;# enable
        mww 0xfca80014 0x00001c06       ;# strobe
        mww 0xfca80014 0x00001c0e
-       while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
+       while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
 
        mww 0xfca80028 0x00000082       ;# enable plltimeen
        mww 0xfca80024 0x00000511       ;# set hclkdiv="/2" & pclkdiv="/2"
 
        mww 0xfca00000 0x00000004       ;# setting SYSCTL to NORMAL mode
-       while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
+       while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
 
        # Select source of DDR clock
        #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1