+# SPDX-License-Identifier: GPL-2.0-or-later
+
uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
jtag_rclk 8
halt
wait_halt 10000
- set rstc_mr_val [expr $::AT91_RSTC_KEY]
- set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
- set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+ set rstc_mr_val $::AT91_RSTC_KEY
+ set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
+ set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
}
mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
- set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
+ set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
- while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
+ while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
- set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
- set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)]
- set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
- set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
- set pllar_val [expr ($pllar_val | $config(master_pll_div))]
+ set pllar_val $::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
+ set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}]
+ set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
+ set pllar_val [expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
+ set pllar_val [expr {$pllar_val | $config(master_pll_div)}]
mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
- while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
+ while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
;# PCK/2 = MCK Master Clock from PLLA
- set mckr_val [expr $::AT91_PMC_CSS_PLLA]
- set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)]
- set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
- set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)]
+ set mckr_val $::AT91_PMC_CSS_PLLA
+ set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}]
+ set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
+ set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}]
mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
- while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
+ while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
- ## switch JTAG clock to highseepd clock
+ ## switch JTAG clock to highspeed clock
jtag_rclk 0
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
arm7_9 fast_memory_access enable
- set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
- set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
+ set rstc_mr_val $::AT91_RSTC_KEY
+ set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
- set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
- mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
- set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
- mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
+ if { [info exists config(sdram_piod)] } {
+ set pdr_addr [expr {$::AT91_PIOD + $::PIO_PDR}]
+ set pudr_addr [expr {$::AT91_PIOD + $::PIO_PUDR}]
+ set asr_addr [expr {$::AT91_PIOD + $::PIO_ASR}]
+ mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
+ mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
+ mww $asr_addr 0xffff0000
+ } else {
+ set pdr_addr [expr {$::AT91_PIOC + $::PIO_PDR}]
+ set pudr_addr [expr {$::AT91_PIOC + $::PIO_PUDR}]
+ mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
+ mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
+ }
mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register