mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
- ## switch JTAG clock to highseepd clock
+ ## switch JTAG clock to highspeed clock
jtag_rclk 0
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
- set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
- mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
- set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
- mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
+ if { [info exists config(sdram_piod)] } {
+ set pdr_addr [expr ($::AT91_PIOD + $::PIO_PDR)]
+ set pudr_addr [expr ($::AT91_PIOD + $::PIO_PUDR)]
+ set asr_addr [expr ($::AT91_PIOD + $::PIO_ASR)]
+ mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
+ mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
+ mww $asr_addr 0xffff0000
+ } else {
+ set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
+ set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
+ mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
+ mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
+ }
mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register