tcl/board: add SPDX tag

[fw/openocd] / tcl / board / tp-link_tl-mr3020.cfg

diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg
index b7d8d5b6150f57354e226cdca88d122f1ea5bab9..1d1d627bc27738a515d683347527e59064ef4f4e 100644 (file)
--- a/tcl/board/tp-link_tl-mr3020.cfg
+++ b/tcl/board/tp-link_tl-mr3020.cfg
@@ -1,38 +1,6 @@
-source [find target/atheros_ar9331.cfg]
-
-proc ar9331_25mhz_pll_init {} {
-       mww 0xb8050008 0x00018004       ;# bypass PLL; AHB_POST_DIV - ratio 4
-       mww 0xb8050004 0x00000352       ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
-       mww 0xb8050000 0x40818000       ;# Power down control for CPU PLL
-                                       ;# OUTDIV | REFDIV | DIV_INT
-       mww 0xb8050010 0x001003e8       ;# CPU PLL Dither FRAC Register
-                                       ;# (disabled?)
-       mww 0xb8050000 0x00818000       ;# Power on | OUTDIV | REFDIV | DIV_INT
-       mww 0xb8050008 0x00008000       ;# remove bypass;
-                                       ;# AHB_POST_DIV - ratio 2
-}
-
-proc ar9331_ddr1_init {} {
-       mww 0xb8000000 0x7fbc8cd0       ;# DDR_CONFIG - lots of DRAM confs
-       mww 0xb8000004 0x9dd0e6a8       ;# DDR_CONFIG2 - more DRAM confs
+# SPDX-License-Identifier: GPL-2.0-or-later
 
-       mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
-       mww 0xb8000008 0x133    ;# mode reg: 0x133 - default
-       mww 0xb8000010 0x1      ;# Forces an MRS update cycl
-       mww 0xb800000c 0x2      ;# Extended mode register value.
-                               ;# default 0x2 - Reset to weak driver, DLL on
-       mww 0xb8000010 0x2      ;# Forces an EMRS update cycle
-       mww 0xb8000010 0x8      ;# Forces a PRECHARGE ALL cycle
-       mww 0xb8000008 0x33     ;# mode reg: remove some bit?
-       mww 0xb8000010 0x1      ;# Forces an MRS update cycl
-       mww 0xb8000014 0x4186   ;# enable refres: bit(14) - set refresh rate
-       mww 0xb800001c 0x8      ;# This register is used along with DQ Lane 0,
-                               ;# DQ[7:0], DQS_0
-       mww 0xb8000020 0x9      ;# This register is used along with DQ Lane 1,
-                               ;# DQ[15:8], DQS_1.
-       mww 0xb8000018 0xff     ;# DDR read and capture bit mask.
-                               ;# Each bit represents a cycle of valid data.
-}
+source [find target/atheros_ar9331.cfg]
 
 $_TARGETNAME configure -event reset-init {
        ar9331_25mhz_pll_init
@@ -42,3 +10,5 @@ $_TARGETNAME configure -event reset-init {
 
 set ram_boot_address 0xa0000000
 $_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0xbf000000 0 0 0 $_TARGETNAME cs0