Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface

[fw/openocd] / tcl / board / stm32h745i-disco.cfg

diff --git a/tcl/board/stm32h745i-disco.cfg b/tcl/board/stm32h745i-disco.cfg
new file mode 100644 (file)
index 0000000..5adcfea
--- /dev/null
+++ b/tcl/board/stm32h745i-disco.cfg
@@ -0,0 +1,45 @@
+# This is a stm32h745i-disco with a single STM32H745XIH6 chip.
+# www.st.com/en/product/stm32h745i-disco.html
+#
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set CHIPNAME stm32h745xih6
+
+# enable stmqspi
+if {![info exists QUADSPI]} {
+       set QUADSPI 1
+}
+
+source [find target/stm32h7x_dual_bank.cfg]
+
+source [find board/stm32h7x_dual_qspi.cfg]
+
+$_CHIPNAME.cpu0 configure -event reset-init {
+       global QUADSPI
+
+       mmw 0x52002000 0x00000004 0x0000000B    ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
+
+       mmw 0x58024400 0x00000001 0x00000018    ;# RCC_CR: HSIDIV=1, HSI on
+       mmw 0x58024410 0x10000000 0xEE000007    ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
+       mww 0x58024418 0x00000040                               ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
+       mww 0x5802441C 0x00000440                               ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
+       mww 0x58024420 0x00000040                               ;# RCC_D3CFGR: D3PPRE=2
+       mww 0x58024428 0x00000040                               ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
+       mmw 0x5802442C 0x0001000C 0x00000002    ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
+       mww 0x58024430 0x01070217                               ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
+       mmw 0x58024400 0x01000000 0                             ;# RCC_CR: PLL1ON=1
+       sleep 1
+       mmw 0x58024410 0x00000003 0                             ;# RCC_CFGR: PLL1 as system clock
+       sleep 1
+
+       adapter speed 24000
+
+       if { $QUADSPI } {
+               qspi_init 1
+       }
+}
+