tcl/target/ti_k3: Rename R5 targets to be more descriptive
[fw/openocd] / tcl / board / stm3210e_eval.cfg
index 83ce488c74602cfbe074b1303baddab18f3d9572..f30253c1166ee231c0670376a58bce6019d14198 100644 (file)
@@ -1,8 +1,63 @@
-# This is an STM32 eval board with a single STM32F103ZE chip on it.
-# http://www.st.com/mcu/contentid-100-110-STM3210E_EVAL.html
+# This is an STM32 eval board with a single STM32F103ZET6 chip.
+# http://www.st.com/internet/evalboard/product/204176.jsp
 
-# increase working area for faster flash programming
+# increase working area to 32KB for faster flash programming
+set WORKAREASIZE 0x8000
 
-set WORKAREASIZE 32768
+source [find target/stm32f1x.cfg]
 
-source [find target/stm32.cfg]
+#
+# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash
+# M29W128GL70ZA6E
+#
+
+set _FLASHNAME $_CHIPNAME.norflash
+flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
+
+proc stm32_enable_fsmc {} {
+
+       echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
+
+       # enable gpio (defg) clocks for fsmc
+       # RCC_APB2ENR
+       mww 0x40021018 0x000001E0
+
+       # enable fsmc clock
+       # RCC_AHBENR
+       mww 0x40021014 0x00000114
+
+       # configure gpio to alternate function
+       # GPIOD_CRL
+       mww 0x40011400 0x44BB44BB
+       # GPIOD_CRH
+       mww 0x40011404 0xBBBBBBBB
+
+       # GPIOE_CRL
+       mww 0x40011800 0xBBBBB444
+       # GPIOE_CRH
+       mww 0x40011804 0xBBBBBBBB
+
+       # GPIOF_CRL
+       mww 0x40011C00 0x44BBBBBB
+       # GPIOF_CRH
+       mww 0x40011C04 0xBBBB4444
+
+       # GPIOG_CRL
+       mww 0x40012000 0x44BBBBBB
+       # GPIOG_CRH
+       mww 0x40012004 0x444444B4
+
+       # setup fsmc timings
+       # FSMC_BCR1
+       mww 0xA0000008 0x00001058
+
+       # FSMC_BTR1
+       mww 0xA000000C 0x10000502
+
+       # FSMC_BCR1 - enable fsmc
+       mww 0xA0000008 0x00001059
+}
+
+$_TARGETNAME configure -event reset-init {
+       stm32_enable_fsmc
+}