target: add generic Xtensa LX support

[fw/openocd] / tcl / board / stm3210e_eval.cfg

diff --git a/tcl/board/stm3210e_eval.cfg b/tcl/board/stm3210e_eval.cfg
index 91807ce3094906861e6bb70d5d4b2ee4a573f1d2..f08e04b0e4d1a4627f71ff2ed298bc6889b2ee8f 100644 (file)
--- a/tcl/board/stm3210e_eval.cfg
+++ b/tcl/board/stm3210e_eval.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # This is an STM32 eval board with a single STM32F103ZET6 chip.
 # http://www.st.com/internet/evalboard/product/204176.jsp
 
@@ -17,11 +19,11 @@ flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
 proc stm32_enable_fsmc {} {
 
        echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
-       
+
        # enable gpio (defg) clocks for fsmc
        # RCC_APB2ENR
        mww 0x40021018 0x000001E0
-       
+
        # enable fsmc clock
        # RCC_AHBENR
        mww 0x40021014 0x00000114
@@ -31,29 +33,29 @@ proc stm32_enable_fsmc {} {
        mww 0x40011400 0x44BB44BB
        # GPIOD_CRH
        mww 0x40011404 0xBBBBBBBB
-       
+
        # GPIOE_CRL
        mww 0x40011800 0xBBBBB444
        # GPIOE_CRH
        mww 0x40011804 0xBBBBBBBB
-       
+
        # GPIOF_CRL
        mww 0x40011C00 0x44BBBBBB
        # GPIOF_CRH
        mww 0x40011C04 0xBBBB4444
-       
+
        # GPIOG_CRL
        mww 0x40012000 0x44BBBBBB
        # GPIOG_CRH
        mww 0x40012004 0x444444B4
-       
+
        # setup fsmc timings
        # FSMC_BCR1
        mww 0xA0000008 0x00001058
-       
+
        # FSMC_BTR1
        mww 0xA000000C 0x10000502
-       
+
        # FSMC_BCR1 - enable fsmc
        mww 0xA0000008 0x00001059
 }