# Bare-bones initialization of core clocks and SDRAM
proc phytec_lpc3250_init { } {
- # Set clock dividers
+ # Set clock dividers
# ARMCLK = 266.5 MHz
# HCLK = 133.25 MHz
# PERIPHCLK = 13.325 MHz
mww 0x400040BC 0
- mww 0x40004050 0x140
+ mww 0x40004050 0x140
mww 0x40004040 0x4D
mww 0x40004058 0x16250
sleep 1 busy
mww 0x40004044 0x106
sleep 1 busy
- mww 0x40004044 0x006
+ mww 0x40004044 0x006
sleep 1 busy
mww 0x40004048 0x2
mww 0x31080008 0
mww 0x40004068 0x1C000
mww 0x31080028 0x11
-
+
mww 0x31080400 0
mww 0x31080440 0
mww 0x31080460 0
mww 0x31080054 1
mww 0x31080058 1
mww 0x3108005C 0
-
+
mww 0x31080100 0x5680
mww 0x31080104 0x302