source [find target/pxa255.cfg]
-jtag_nsrst_delay 250
+adapter srst delay 250
jtag_ntrst_delay 250
# NOTE: until after pinmux and such are set up, only CS0 is
# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
# each bank is 32-bits wide, two 16-bit chips in parallel
-flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-flash bank cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash0
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+set _FLASHNAME $_CHIPNAME.flash1
+flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
# CS2 low -- FPGA registers
# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
proc lubbock_init {target} {
- puts "Initialize PXA255 Lubbock board"
+ echo "Initialize PXA255 Lubbock board"
# (1) pinmux