cfg: ftdi icdi enable srst open drain config

[fw/openocd] / tcl / board / imx35pdk.cfg

diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index e5891c8bf4b18faa5a34626adc63ec8f471837bc..b5aa752fa248ec86bd30f9a56a5a785bb2d428fd 100644 (file)
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -3,6 +3,10 @@ source [find target/imx35.cfg]
 source [find target/imx.cfg]
 $_TARGETNAME configure -event reset-init { imx35pdk_init }
 
+# Stick to *really* low clock rate or reset will fail
+# without RTCK / RCLK
+jtag_rclk 10
+
 proc imx35pdk_init { } {
        
        imx3x_reset
@@ -23,8 +27,8 @@ proc imx35pdk_init { } {
        mww 0x53f00004 0x77777777
        
        # clock setup
-       mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
-       mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
+       mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
+       mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
        
        #=================================================
        # WEIM config
@@ -118,8 +122,8 @@ proc imx35pdk_init { } {
        mww 0x43FAC474 0x00000006
        mww 0x43FAC478 0x00000006
        mww 0x43FAC47c 0x00000006
-       mww 0x43FAC480 0x00000006       # CSD0
-       mww 0x43FAC484 0x00000006       # CSD1
+       mww 0x43FAC480 0x00000006       ;# CSD0
+       mww 0x43FAC484 0x00000006       ;# CSD1
        mww 0x43FAC488 0x00000006
        mww 0x43FAC48c 0x00000006
        mww 0x43FAC490 0x00000006
@@ -127,12 +131,12 @@ proc imx35pdk_init { } {
        mww 0x43FAC498 0x00000006
        mww 0x43FAC49c 0x00000006
        mww 0x43FAC4A0 0x00000006       
-       mww 0x43FAC4A4 0x00000006       # RAS
-       mww 0x43FAC4A8 0x00000006       # CAS
-       mww 0x43FAC4Ac 0x00000006       # SDWE
-       mww 0x43FAC4B0 0x00000006       # SDCKE0
-       mww 0x43FAC4B4 0x00000006  # SDCKE1
-       mww 0x43FAC4B8 0x00000002  # SDCLK
+       mww 0x43FAC4A4 0x00000006       ;# RAS
+       mww 0x43FAC4A8 0x00000006       ;# CAS
+       mww 0x43FAC4Ac 0x00000006       ;# SDWE
+       mww 0x43FAC4B0 0x00000006       ;# SDCKE0
+       mww 0x43FAC4B4 0x00000006  ;# SDCKE1
+       mww 0x43FAC4B8 0x00000002  ;# SDCLK
        
        # SDQS0 through SDQS3
        mww 0x43FAC4Bc 0x00000082
@@ -207,7 +211,7 @@ proc imx35pdk_init { } {
        # DDR2 : Load reg EMR1 -- OCD default
        mwb 0x82000780 0xda
        # DDR2 : Load reg EMR1 -- OCD exit
-       mwb 0x82000400 0xda     # ODT disabled
+       mwb 0x82000400 0xda     ;# ODT disabled
        
        # ESD_ESDCTL0 : select normal-operation mode
        # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
@@ -225,10 +229,10 @@ proc imx35pdk_init { } {
        # Adjust the ESDCDLY5 register
        #***********************************************
        # Vary DQS_ABS_OFFSET5 for writes
-       mww 0xB8001020 0x00F48000       # this is the default value
-       mww 0xB8001024 0x00F48000       # this is the default value
-       mww 0xB8001028 0x00F48000       # this is the default value
-       mww 0xB800102c 0x00F48000       # this is the default value
+       mww 0xB8001020 0x00F48000       ;# this is the default value
+       mww 0xB8001024 0x00F48000       ;# this is the default value
+       mww 0xB8001028 0x00F48000       ;# this is the default value
+       mww 0xB800102c 0x00F48000       ;# this is the default value
        
        
        #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)