tcl/board: add SPDX tag

[fw/openocd] / tcl / board / icnova_sam9g45_sodimm.cfg

diff --git a/tcl/board/icnova_sam9g45_sodimm.cfg b/tcl/board/icnova_sam9g45_sodimm.cfg
index bf70cca9ae7ec55b1e79f254453ee6dc2933ad09..7efa8c2b528b82cd647be418b08f9a61ac67746d 100644 (file)
--- a/tcl/board/icnova_sam9g45_sodimm.cfg
+++ b/tcl/board/icnova_sam9g45_sodimm.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #################################################################################################
 #                                                                                                                                              #
 # Author: Lars Poeschel (larsi@wh2.tu-dresden.de)                                                                                              #
@@ -43,9 +45,7 @@ flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
 
 
 proc read_register {register} {
-        set result ""
-        mem2array result 32 $register 1
-        return $result(0)
+       return [read_memory $register 32 1]
 }
 
 proc at91sam9g45_start { } {
@@ -89,27 +89,27 @@ proc at91sam9g45_init { } {
        # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
 
        mww 0xfffffc20 0x00004001
-       while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
+       while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
 
        # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
        # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
 
        #mww 0xfffffc28 0x202a3f01
        mww 0xfffffc28 0x20c73f03
-       while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
+       while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
 
        # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
        # Wait for MCKRDY signal from PMC_SR to assert.
 
        #mww 0xfffffc30 0x00000101
        mww 0xfffffc30 0x00001301
-       while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+       while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
        # Now change PMC_MCKR register to select PLLA.
        # Wait for MCKRDY signal from PMC_SR to assert.
 
        mww 0xfffffc30 0x00001302
-       while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+       while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
 
        # Processor and master clocks are now operating and stable at maximum frequency possible:
        #       -> MCLK = 132.096 MHz
@@ -214,7 +214,7 @@ proc at91sam9g45_init { } {
        sleep 1
 
        # 9. Enable DLL Reset (set DLL bit)
-       set CR  [expr [read_register 0xffffe608] | 0x80]
+       set CR  [expr {[read_register 0xffffe608] | 0x80}]
        mww 0xffffe608 $CR
 
        # 10. mode register cycle to reset the DLL
@@ -236,7 +236,7 @@ proc at91sam9g45_init { } {
        # 12.3 delay 10 cycles
 
        # 13. disable DLL reset (clear DLL bit)
-       set CR  [expr [read_register 0xffffe608] & 0xffffff7f]
+       set CR  [expr {[read_register 0xffffe608] & 0xffffff7f}]
        mww 0xffffe608 $CR
 
        # 14. mode register set cycle
@@ -244,7 +244,7 @@ proc at91sam9g45_init { } {
        mww 0x70000000 0x1
 
        # 15. program OCD field (set OCD bits)
-       set CR  [expr [read_register 0xffffe608] | 0x7000]
+       set CR  [expr {[read_register 0xffffe608] | 0x7000}]
        mww 0xffffe608 $CR
 
        # 16. (EMRS1)
@@ -253,7 +253,7 @@ proc at91sam9g45_init { } {
        # 16.1 delay 2 cycles
 
        # 17. disable OCD field (clear OCD bits)
-       set CR  [expr [read_register 0xffffe608] & 0xffff8fff]
+       set CR  [expr {[read_register 0xffffe608] & 0xffff8fff}]
        mww 0xffffe608 $CR
 
        # 18. (EMRS1)
@@ -274,5 +274,3 @@ proc at91sam9g45_init { } {
 
        arm7_9 fast_memory_access enable
 }
-
-