# Set reset type
#reset_config srst_only
-adapter_khz 3000
+adapter speed 3000
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
$_TARGETNAME configure -event "reset-assert" {
- echo "Reseting ...."
+ echo "Resetting ...."
#cortex_a dbginit
}
; # ARM errata ID #468414
set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
+ arm mcr 15 0 1 0 1 [expr {$tR | (1<<5)}] ; # enable L1NEON bit
init_l2cc
init_aips
arm core_state arm
jtag_rclk 3000
-# adapter_khz 3000
+# adapter speed 3000
}
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
- arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
+ arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
; #orr r0, r0, #(1 << 22) /* disable write allocate */
; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
+ arm mcr 15 1 9 0 2 [expr {0xC4 | (1<<24) | (1<<23) | (1<<22)}]
}
set VAL 0x77777777
# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS1_BASE_ADDR + 0x4}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x0}] $VAL
+ mww [expr {$AIPS2_BASE_ADDR + 0x4}] $VAL
# dap apsel 0
}
proc init_clock { } {
global AIPS1_BASE_ADDR
global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
+ set CCM_BASE_ADDR [expr {$AIPS1_BASE_ADDR + 0x000D4000}]
set CLKCTL_CCSR 0x0C
set CLKCTL_CBCDR 0x14
set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
+ set PLL1_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00080000}]
+ set PLL2_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00084000}]
+ set PLL3_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x00088000}]
+ set PLL4_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x0008C000}]
set CLKCTL_CSCMR1 0x1C
set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
+ set PLATFORM_BASE_ADDR [expr {$AIPS2_BASE_ADDR + 0x000A0000}]
set CLKCTL_CSCDR1 0x24
set CLKCTL_CCDR 0x04
; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x4
return
echo "not returned"
setup_pll $PLL3_BASE_ADDR 400
; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00015154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x02888945 | (1<<16)}]
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL2_BASE_ADDR 400
; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCDR}] [expr {0x00808145 | (2<<10) | (9<<16) | (1<<19)}]
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
+ while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
setup_pll $PLL3_BASE_ADDR 216
setup_pll $PLL4_BASE_ADDR 455
; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
+ mww [expr {$PLATFORM_BASE_ADDR + 0x14}] 0x00000124
- mww [expr $CCM_BASE_ADDR + 0x10] 0
+ mww [expr {$CCM_BASE_ADDR + 0x10}] 0
; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x6C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x70}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x74}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x78}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x7C}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x80}] 0xFFFFFFFF
+ mww [expr {$CCM_BASE_ADDR + 0x84}] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
+ mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCDR}] 0x00000
; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
+ mww [expr {$CCM_BASE_ADDR + 0x60}] [expr {0x000A0000 & 0x00000F0}]
}
set PLL_DP_HFS_MFN 0x24
if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
+ set DP_OP [expr {(10 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {12 - 1}]
set DP_MFN 5
} elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 41
} elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(7 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 7
} elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 1
} elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
+ set DP_OP [expr {(6 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {96 - 1}]
set DP_MFN 89
} elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
+ set DP_OP [expr {(5 << 4) + ((1 - 1) << 0)}]
+ set DP_MFD [expr {24 - 1}]
set DP_MFN 13
} elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {48 - 1}]
set DP_MFN 71
} elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
+ set DP_OP [expr {(8 << 4) + ((2 - 1) << 0)}]
+ set DP_MFD [expr {3 - 1}]
set DP_MFN 1
} elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
+ set DP_OP [expr {(6 << 4) + ((3 - 1) << 0)}]
+ set DP_MFD [expr {4 - 1}]
set DP_MFN 3
} else {
error "Error (setup_dll): clock not found!"
}
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ mww [expr {$PLL_ADDR + $PLL_DP_CONFIG}] 0x2
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_OP}] $DP_OP
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_MFD}] $DP_MFD
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFD}] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_MFN}] $DP_MFN
+ mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
+ mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
+ while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
}
proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
+ return [expr {(($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)}]
}