Add EfikaMX smarttop board support

[fw/openocd] / tcl / board / hitex_lpc2929.cfg

diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index d0b28647cf32bd230f1ec0a6f1f61e62e41e7313..d9ca1109e359461d960b99c2bd8df0ef948dcde6 100644 (file)
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -2,12 +2,12 @@
 # http://www.hitex.com/
 
 # Delays on reset lines
-jtag_nsrst_delay 50
+adapter_nsrst_delay 50
 jtag_ntrst_delay 1
 
 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
 # Adaptive clocking through RTCK is not supported.
-jtag_khz 2000
+adapter_khz 2000
 
 # Target device: LPC29xx with ETB
 # The following variables are used by the LPC2900 script:
@@ -24,11 +24,12 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-
 # Event handlers
 $_TARGETNAME configure -event reset-start {
   # Back to the slow JTAG clock
-  jtag_khz 2000
+  adapter_khz 2000
 }
 
 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
-flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
 
 
 $_TARGETNAME configure -event reset-init {
@@ -45,7 +46,7 @@ $_TARGETNAME configure -event reset-init {
   mww 0xFFFF8070 0x02000000     # SYS_CLK_CONF: PLL
 
   # Increase JTAG speed
-  jtag_khz 6000
+  adapter_khz 6000
 
   # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
   mww 0xE0001138 0x0000001F     # P1.14 = D0