# http://www.hitex.com/
# Delays on reset lines
-adapter_nsrst_delay 50
+adapter srst delay 50
jtag_ntrst_delay 1
# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
+adapter speed 2000
# Target device: LPC29xx with ETB
# The following variables are used by the LPC2900 script:
# Event handlers
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
- adapter_khz 2000
+ adapter speed 2000
}
# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
$_TARGETNAME configure -event reset-init {
# Flash
- mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
+ mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not cached
# Use PLL
mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
# Increase JTAG speed
- adapter_khz 6000
+ adapter speed 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
mww 0xE0001138 0x0000001F ;# P1.14 = D0
mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2
}
-