flash/nor/at91samd: Use 32-bit register writes for ST-Link compat

[fw/openocd] / tcl / board / hilscher_nxhx10.cfg

diff --git a/tcl/board/hilscher_nxhx10.cfg b/tcl/board/hilscher_nxhx10.cfg
index 7ff99165a9007ee6ddf17858889226d7604866bc..e116a6cc327d7382a89530f6eabc15fcd46c3f63 100644 (file)
--- a/tcl/board/hilscher_nxhx10.cfg
+++ b/tcl/board/hilscher_nxhx10.cfg
@@ -1,3 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 ################################################################################
 # Author: Michael Trensch (MTrensch@googlemail.com)
 ################################################################################
@@ -26,15 +28,13 @@ proc flash_init { } {
 }
 
 proc mread32 {addr} {
-  set value(0) 0
-  mem2array value 32 $addr 1
-  return $value(0)
+  return [read_memory $addr 32 1]
 }
 
 proc init_clocks { } {
   puts "Enabling all clocks "
   set accesskey [mread32 0x101c0070]
-  mww  0x101c0070 [expr $accesskey]
+  mww  0x101c0070 $accesskey
 
   mww  0x101c0028 0x00007511
 }
@@ -42,7 +42,7 @@ proc init_clocks { } {
 proc init_sdrambus { } {
   puts "Initializing external SDRAM Bus 16 Bit "
   set accesskey [mread32 0x101c0070]
-  mww  0x101c0070 [expr $accesskey]
+  mww  0x101c0070 $accesskey
   mww  0x101c0C40 0x00000050
 
   puts "Configuring SDRAM controller for K4S561632E (32MB) "
@@ -79,4 +79,4 @@ $_TARGETNAME configure -event reset-init {
 #flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
 
 init
-reset init
\ No newline at end of file
+reset init