proc init_board {} {
# Delays on reset lines
- adapter_nsrst_delay 500
+ adapter srst delay 500
jtag_ntrst_delay 1
# Adaptive JTAG clocking through RTCK.
global _CHIPNAME
# A working area will help speeding the flash programming
- $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
+ $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr {0x10000-0x200-0x20}] -work-area-backup 0
# External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
#
proc enable_pll {} {
# Disconnect PLL in case it is already connected
- if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
+ if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
# Disconnect it, but leave it enabled
# (This MUST be done in two steps)
mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
-