+# SPDX-License-Identifier: GPL-2.0-or-later
+
# The Cogent CSB732 board has a single i.MX35 chip
source [find target/imx35.cfg]
# Determined by trial and error
reset_config trst_and_srst combined
-jtag_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
# We assume the interpreter latency is enough.
# Allow access to all coprocessors
- arm11 mcr imx35.cpu 15 0 15 1 0 0x2001
+ arm mcr 15 0 15 1 0 0x2001
# Disable MMU, caches, write buffer
- arm11 mcr imx35.cpu 15 0 1 0 0 0x78
+ arm mcr 15 0 1 0 0 0x78
# Grant manager access to all domains
- arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF
+ arm mcr 15 0 3 0 0 0xFFFFFFFF
# Set ARM clock to 532 MHz, AHB to 133 MHz
mww 0x53F80004 0x1000